17 FN7870.0 June 21, 2011 Applications Information VLOGIC Requirements<" />
參數(shù)資料
型號: ISL23325UFVZ-T7A
廠商: Intersil
文件頁數(shù): 9/20頁
文件大?。?/td> 0K
描述: IC DGTL POT DUAL 50K 14TSSOP
標(biāo)準(zhǔn)包裝: 1
系列: XDCP™
接片: 256
電阻(歐姆): 50k
電路數(shù): 2
溫度系數(shù): 標(biāo)準(zhǔn)值 65 ppm/°C
存儲器類型: 易失
接口: I²C,2 線串口
電源電壓: 1.2 V ~ 5.5 V,1.7 V ~ 5.5 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 14-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 14-TSSOP
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: ISL23325UFVZ-T7ADKR
ISL23325
17
FN7870.0
June 21, 2011
Applications Information
VLOGIC Requirements
VLOGIC should be powered continuously during normal operation.
In a case where turning VLOGIC OFF is necessary, it is
recommended to ground the VLOGIC pin of the ISL23325.
Grounding the VLOGIC pin or both VLOGIC and VCC does not affect
other devices on the same bus. It is good practice to put a 1F
cap in parallel to 0.1F as close to the VLOGIC pin as possible.
VCC Requirements and Placement
It is recommended to put a 1F capacitor in parallel with 0.1F
decoupling capacitor close to the VCC pin.
Wiper Transition
When stepping up through each tap in voltage divider mode,
some tap transition points can result in noticeable voltage
transients, or overshoot/undershoot, resulting from the sudden
transition from a very low impedance “make” to a much higher
impedance “break” within a short period of time (<1s). There
are several code transitions such as 0Fh to 10h, 1Fh to 20h,...,
EFh to FFh, which have higher transient glitch. Note, that all
switching transients will settle well within the settling time as
stated in the datasheet. A small capacitor can be added
externally to reduce the amplitude of these voltage transients.
However, that will also reduce the useful bandwidth of the circuit,
thus may not be a good solution for some applications. It may be
a good idea, in that case, to use fast amplifiers in a signal chain
for fast recovery.
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