16 FN7887.0 July 26, 2011 Write Operation A Write operation requires a START condition, followed by a valid Identification Byte, a val" />
參數(shù)資料
型號(hào)： ISL23318WFUZ-T7A
廠商： Intersil
文件頁(yè)數(shù)： 8/19頁(yè)
文件大小： 0K
描述： IC DGTL POT 1CH 10K 10MSOP
標(biāo)準(zhǔn)包裝： 1
系列： XDCP™
接片： 128
電阻（歐姆）： 10k
電路數(shù)： 1
溫度系數(shù)： 標(biāo)準(zhǔn)值 175 ppm/°C
存儲(chǔ)器類(lèi)型： 易失
接口： I²C（設(shè)備位址）
電源電壓： 1.2 V ~ 5.5 V，1.7 V ~ 5.5 V
工作溫度： -40°C ~ 125°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 10-TFSOP，10-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 10-MSOP
包裝： 標(biāo)準(zhǔn)包裝
其它名稱(chēng)： ISL23318WFUZ-T7ADKR
ISL23318
16
FN7887.0
July 26, 2011
Write Operation
A Write operation requires a START condition, followed by a valid
Identification Byte, a valid Address Byte, a Data Byte, and a STOP
condition. After each of the three bytes, the ISL23318 responds
with an ACK. The data is transferred from I2C block to the
corresponding register at the 9th clock of the data byte and
device enters its standby state (see Figures 28 and 29).
Read Operation
A Read operation consists of a three byte instruction followed by
one or more Data Bytes (see Figure 30). The master initiates the
operation issuing the following sequence: a START, the
Identification byte with the R/W bit set to “0”, an Address Byte, a
second START, and a second Identification byte with the R/W bit
set to “1”. After each of the three bytes, the ISL23318 responds
with an ACK; then the ISL23318 transmits Data Byte. The master
terminates the read operation issuing a NACK (ACK) and a STOP
condition following the last bit of the last Data Byte (see
Figure 30).
Applications Information
VLOGIC Requirements
It is recommended to keep VLOGIC powered all the time during
normal operation. In a case where turning VLOGIC OFF is
necessary, it is recommended to ground the VLOGIC pin of the
ISL23318. Grounding the VLOGIC pin or both VLOGIC and VCC does
not affect other devices on the same bus. It is good practice to
put a 1F cap in parallel to 0.1F as close to the VLOGIC pin as
possible.
VCC Requirements and Placement
It is recommended to put a 1F capacitor in parallel with 0.1F
decoupling capacitor close to the VCC pin.
Wiper Transition
When stepping up through each tap in voltage divider mode,
some tap transition points can result in noticeable voltage
transients, or overshoot/undershoot, resulting from the sudden
transition from a very low impedance “make” to a much higher
impedance “break” within a short period of time (<1s). There
are several code transitions such as 0Fh to 10h, 1Fh to 20h,...,
7Eh to 7Fh, which have higher transient glitch. Note that all
switching transients will settle well within the settling time as
stated in the datasheet. A small capacitor can be added
externally to reduce the amplitude of these voltage transients.
However, that will also reduce the useful bandwidth of the circuit,
thus may not be a good solution for some applications. It may be
a good idea, in that case, to use fast amplifiers in a signal chain
for fast recovery.
SIGNALS
FROM THE
MASTER
SIGNALS FROM
THE SLAVE
SIGNAL AT SDA
S
T
A
R
T
IDENTIFICATION
BYTE WITH
R/W = 0
ADDRESS
BYTE
A
C
K
A
C
K
10
1
00
S
T
O
P
A
C
K
1
IDENTIFICATION
BYTE WITH
R/W = 1
A
C
K
S
T
A
R
T
LAST READ
DATA BYTE
FIRST READ
DATA BYTE
A
C
K
00 0
A0
A1
A0
A1
FIGURE 30. READ SEQUENCE
A
C
K
0
10 1 0
READ
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