- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384519 > ISL22449 (Intersil Corporation) Low Noise, Low Power, SPI Bus, 128 Taps, Wiper Only(低噪聲,低功率，SPI總線, 128抽頭電位器) PDF資料下載
參數(shù)資料
| 型號(hào)： | ISL22449 |
| 廠商： | Intersil Corporation |
| 英文描述： | Low Noise, Low Power, SPI Bus, 128 Taps, Wiper Only(低噪聲,低功率，SPI總線, 128抽頭電位器) |
| 中文描述： | 低噪聲，低功耗，SPI總線，128抽頭，雨刷，只有（低噪聲，低功率和SPI總線，128抽頭電位器） |
| 文件頁(yè)數(shù)： | 9/12頁(yè) |
| 文件大?。?/td> | 356K |
| 代理商： | ISL22449 |
9
FN6333.2
September 15, 2006
Serial Data Output (SDO)
The SDO is an open drain serial data output pin. During a
read cycle, the data bits are shifted out at the falling edge of
the serial clock SCK, while the CS input is low.
SDO requires an external pull-up resistor for proper
operation.
Serial Data Input (SDI)
The SDI is the serial data input pin for the SPI interface. It
receives device address, operation code, wiper address and
data from the SPI external host device. The data bits are
shifted in at the rising edge of the serial clock SCK, while the
CS input is low.
Chip Select (CS
)
CS LOW enables the ISL22449, placing it in the active
power mode. A HIGH to LOW transition on CS is required
prior to the start of any operation after power up. When CS is
HIGH, the ISL22449 is deselected and the SDO pin is at
high impedance, and (unless an internal write cycle is
underway) the device will be in the standby state.
Principles of Operation
The ISL22449 is an integrated circuit incorporating four
DCPs with its associated registers, non-volatile memory and
the SPI serial interface providing direct communication
between host and potentiometers and memory. The resistor
array is comprised of individual resistors connected in
series. At either end of the array and between each resistor
is an electronic switch that transfers the potential at that
point to the wiper.
The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions.
When the device is powered down, the last value stored in
IVRi will be maintained in the non-volatile memory. When
power is restored, the contents of the IVRi is recalled and
loaded into the corresponding WRi to set the wiper to the
initial value.
DCP Description
Each DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each
DCP are equivalent to the fixed terminals of a mechanical
potentiometer and internally connected to Vcc and GND.
The RW pin of each DCP is connected to intermediate
nodes, and is equivalent to the wiper terminal of a
mechanical potentiometer. The position of the wiper terminal
within the DCP is controlled by volatile Wiper Register (WR).
Each DCP has its own WR. When the WR of a DCP contains
all zeroes (WR[6:0]= 00h), its wiper terminal (RW) is closest
to GND. When the WR register of a DCP contains all ones
(WR[6:0]= 7Fh), its wiper terminal (RW) is closest to V
CC
. As
the value of the WR increases from all zeroes (0) to all ones
(127 decimal), the wiper moves monotonically from the
position closest to GND to the closest to V
CC
.
While the ISL22449 is being powered up, all four WRs are
reset to 40h (64 decimal), which locates RW roughly at the
center between GND and V
CC
. After the power supply
voltage becomes large enough for reliable non-volatile
memory reading, all WRs will be reload with the value stored
in corresponding non-volatile Initial Value Registers (IVRs).
The SPI interface register address bits have to be set to
0000b, 0001b, 0010b or 0011b to access the WR of DCP0,
DCP1, DCP2 or DCP3 respectively. The WRi and IVRi can
be read or written to directly using the SPI serial interface as
described in the following sections.
Memory Description
The ISL22449 contains seven non-volatile and five volatile
8-bit registers. The memory map of ISL22449 is on Table 1.
The four non-volatile registers (IVRi) at address 0, 1, 2 and
3, contain initial wiper value and volatile registers (WRi)
contain current wiper position. In addition, three non-volatile
General Purpose registers from address 4 to address 6 are
available.
The non-volatile IVRi and volatile WRi registers are
accessible with the same address.
The Access Control Register (ACR) contains information
and control bits described below in Table 2.
The VOL bit (ACR[7]) determines whether the access is to
wiper registers WR or initial value registers IVR.
If VOL bit is 0, the non-volatile IVR register is accessible. If
VOL bit is 1, only the volatile WRi is accessible. Note, value
is written to IVRi register also is written to the WRi. The
default value of this bit is 0.
The SHDN bit (ACR[6]) disables or enables Shutdown
mode. This bit is logically OR’d with SHDN pin. When this bit
is 0, DCPs are in Shutdown mode. Default value of SHDN bit
is 1.
The WIP bit (ACR[5]) is read only bit. It indicates that non-
volatile write operation is in progress. The WIP bit can be
TABLE 1. MEMORY MAP
ADDRESS
NON-VOLATILE
VOLATILE
8
—
ACR
7
Reserved
6
5
4
General Purpose
General Purpose
General Purpose
Not Available
Not Available
Not Available
3
2
1
0
IVR3
IVR2
IVR1
IVR0
WR3
WR2
WR1
WR0
TABLE 2. ACCESS CONTROL REGISTER (ACR)
BIT #
7
6
5
4
3
2
1
0
Bit Name
VOL
SHDN
WIP
0
0
0
0
0
ISL22449
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISL28156 | 39μA Micropower Single and Dual Precision Rail-to-Rail Input-Output (RRIO) Low Input Bias Current Op Amps(39μA，微功率單/雙精度軌對(duì)軌輸入-輸出(RRIO)，低輸入偏流運(yùn)放) |
| ISL28256 | 39μA Micropower Single and Dual Precision Rail-to-Rail Input-Output (RRIO) Low Input Bias Current Op Amps(39μA，微功率單/雙精度軌對(duì)軌輸入-輸出(RRIO)，低輸入偏流運(yùn)放) |
| ISL37105P-CD | PRISM 3 11 Mbps Wireless Local Area Network PCMCIA |
| ISL37105P-EVAL | PRISM 3 11 Mbps Wireless Local Area Network PCMCIA |
| ISL37200M-CD | PRISM 3 11 Mbps Wireless Local Area Network miniPCI |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISL22449UFV14Z | 功能描述:IC POT DGTL 128TP LN LP 14-TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:XDCP™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 接片:32 電阻（歐姆）:50k 電路數(shù):1 溫度系數(shù):標(biāo)準(zhǔn)值 50 ppm/°C 存儲(chǔ)器類型:易失 接口:3 線串行（芯片選擇，遞增，增/減） 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 細(xì)型，TSOT-23-6 供應(yīng)商設(shè)備封裝:TSOT-23-6 包裝:帶卷 (TR) |
| ISL22449UFV14Z-TK | 功能描述:IC POT DGTL 128TP LN LP 14-TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:XDCP™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 接片:32 電阻（歐姆）:50k 電路數(shù):1 溫度系數(shù):標(biāo)準(zhǔn)值 50 ppm/°C 存儲(chǔ)器類型:易失 接口:3 線串行（芯片選擇，遞增，增/減） 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 細(xì)型，TSOT-23-6 供應(yīng)商設(shè)備封裝:TSOT-23-6 包裝:帶卷 (TR) |
| ISL22449WFV14Z | 功能描述:IC POT DGTL 128TP LN LP 14-TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:XDCP™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 接片:32 電阻（歐姆）:50k 電路數(shù):1 溫度系數(shù):標(biāo)準(zhǔn)值 50 ppm/°C 存儲(chǔ)器類型:易失 接口:3 線串行（芯片選擇，遞增，增/減） 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 細(xì)型，TSOT-23-6 供應(yīng)商設(shè)備封裝:TSOT-23-6 包裝:帶卷 (TR) |
| ISL22449WFV14Z-TK | 功能描述:IC POT DGTL 128TP LN LP 14-TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:XDCP™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 接片:32 電阻（歐姆）:50k 電路數(shù):1 溫度系數(shù):標(biāo)準(zhǔn)值 50 ppm/°C 存儲(chǔ)器類型:易失 接口:3 線串行（芯片選擇，遞增，增/減） 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 細(xì)型，TSOT-23-6 供應(yīng)商設(shè)備封裝:TSOT-23-6 包裝:帶卷 (TR) |
| ISL22511 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Low Noise, Low Power, 32 Taps, Push Button Controlled Potentiometer Single Push Button Controlled Potentiometer XDCP |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。