參數(shù)資料
型號(hào): ISL22416
廠商: Intersil Corporation
英文描述: Low Noise, Low Power, SPI Bus, 128 Taps(低噪聲,低功率,SPI總線, 128抽頭電位器)
中文描述: 低噪聲,低功耗,SPI總線,128絲錐(低噪聲,低功率和SPI總線,128抽頭電位器)
文件頁(yè)數(shù): 11/13頁(yè)
文件大?。?/td> 463K
代理商: ISL22416
11
FN6227.0
June 23, 2006
the IVR or the WR register (depends of VOL bit at ACR). If
the R1 bit is 1 and R0 bit is 0, then the operation is on the
ACR.
Write Operation
A Write operation to the ISL22416 is a three-byte operation.
It requires first, the CS transition from HIGH to LOW, then a
valid Identification Byte, then a valid instruction byte followed
by Data Byte is sent to SDI pin. The host terminates the write
operation by pulling the CS pin from LOW to HIGH. For a
write to address 0 (WR), the byte at address 2 (ACR<7>)
determines if the Data Byte is to be written to volatile or both
volatile and non-volatile registers. Refer to “Memory
Description” and Figure 16.
The internal non-volatile write cycle starts after rising edge of
CS and takes up to 20ms.
Read Operation
A read operation to the ISL22416 is a three byte operation. It
requires first, the CS transition from HIGH to LOW, then a
valid Identification Byte, then a valid instruction byte followed
by “dummy” Data Byte is sent to SDI pin. The SPI host reads
the data from SDO pin on falling edge of SCK. The host
terminates the read operation by pulling the CS pin from
LOW to HIGH (see Figure 17).
In order to read back the non-volatile IVR, it is reccomended
that the application reads the ACR first to verify the WIP bit
is 0. If the WIP bit (ACR[5]) is not 0, the host should repeat
its reading sequence again.
Applications Information
Communicating with ISL22416
Communication with ISL22416 proceeds using SPI interface
through the ACR (address 10b), IVR (address 00b) and WR
(address 00b) registers.
The wiper of the potentiometer is controlled by the WR
register. Writes and reads can be made directly to this
register to control and monitor the wiper position without any
non-volatile memory changes. This is done by setting MSB
bit at address 10b to 1.
The non-volatile IVR stores the power up value of the wiper.
IVR is accessible when MSB bit at address 10b is set to 0.
Writing a new value to the IVR register will set a new power
up position for the wiper. Also, writing to this register will load
the same value into the WR as the IVR. Reading from the
IVR will not change the WR, if its contents are different.
0
1
0
1
0
0
I3
I2
I1
I0
0
0
R1 R0
SCK
SDI
0
D6 D5 D4 D3 D2
D1 D0
CS
0
0
0
FIGURE 16. THREE BYTE WRITE SEQUENCE
0
1
0
1
0
0
I3
I2
I1
I0
0
0
R1 R0
SCK
SDI
CS
0
0
SDO
0
D6 D5 D4 D3 D2
D1 D0
Don’t Care
0
FIGURE 17. THREE BYTE READ SEQUENCE
ISL22416
相關(guān)PDF資料
PDF描述
ISL22419 Low Noise, Low Power, SPI Bus, 128 Taps, Wiper Only(低噪聲,低功率,SPI總線, 128抽頭電位器)
ISL22426 Low Noise, Low Power, SPI Bus, 128 Taps(低噪聲,低功率,SPI總線, 128抽頭電位器)
ISL22429 Low Noise, Low Power, SPI Bus, 128 Taps, Wiper Only(低噪聲,低功率,SPI總線, 128抽頭電位器)
ISL22446 Low Noise, Low Power, SPI Bus, 128 Taps(低噪聲,低功率,SPI總線, 128抽頭電位器)
ISL22449 Low Noise, Low Power, SPI Bus, 128 Taps, Wiper Only(低噪聲,低功率,SPI總線, 128抽頭電位器)
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