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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | ISL22346WFRT20Z-TK |
| 寤犲晢锛� | Intersil |
| 鏂囦欢闋佹暩(sh霉)锛� | 13/16闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC POT DGTL 128TP LN LP 20-TQFN |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 1,000 |
| 绯诲垪锛� | XDCP™ |
| 鎺ョ墖锛� | 128 |
| 闆婚樆锛堟瓙濮嗭級锛� | 10k |
| 闆昏矾鏁�(sh霉)锛� | 4 |
| 婧害绯绘暩(sh霉)锛� | 妯�(bi膩o)婧�(zh菙n)鍊� ±50 ppm/°C |
| 瀛樺劜(ch菙)鍣ㄩ鍨嬶細 | 闈炴槗澶� |
| 鎺ュ彛锛� | I²C锛堣ō(sh猫)鍌欎綅鍧€锛� |
| 闆绘簮闆诲锛� | 2.7 V ~ 5.5 V |
| 宸ヤ綔婧害锛� | -40°C ~ 125°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 20-WFQFN 瑁搁湶鐒婄洡 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 20-TQFN锛�4x4锛� |
| 鍖呰锛� | 甯跺嵎 (TR) |
6
FN6177.2
September 3, 2009
VCCRamp VCC Ramp Rate
0.2
V/ms
tD
Power-up Delay
VCC above Vpor, to DCP Initial Value
Register recall completed, and I2C Interface
in standby state
3ms
EEPROM SPECIFICATION
EEPROM Endurance
1,000,000
Cycles
EEPROM Retention
Temperature T < +55掳C
50
Years
tWC
(Note 19)
Non-volatile Write Cycle Time
12
20
ms
SERIAL INTERFACE SPECIFICATIONS
VIL
A2, A1, A0, SHDN, SDA, and SCL
Input Buffer LOW Voltage
-0.3
0.3*VCC
V
VIH
A2, A1, A0, SHDN, SDA, and SCL
Input Buffer HIGH Voltage
0.7*VCC
VCC + 0.3
V
Hysteresis
SDA and SCL Input Buffer Hysteresis
0.05*VCC
V
VOL
SDA Output Buffer LOW Voltage,
Sinking 4mA
00.4
V
Cpin
(Note 20)
A2, A1, A0, SHDN, SDA, and SCL Pin
Capacitance
10
pF
fSCL
SCL Frequency
400
kHz
tsp
Pulse Width Suppression Time at
SDA and SCL Inputs
Any pulse narrower than the max spec is
suppressed
50
ns
tAA
SCL Falling Edge to SDA Output Data
Valid
SCL falling edge crossing 30% of VCC, until
SDA exits the 30% to 70% of VCC window
900
ns
tBUF
Time the Bus Must be Free Before the
Start of a New Transmission
SDA crossing 70% of VCC during a STOP
condition, to SDA crossing 70% of VCC
during the following START condition
1300
ns
tLOW
Clock LOW Time
Measured at the 30% of VCC crossing
1300
ns
tHIGH
Clock HIGH Time
Measured at the 70% of VCC crossing
600
ns
tSU:STA
START Condition Setup Time
SCL rising edge to SDA falling edge; both
crossing 70% of VCC
600
ns
tHD:STA
START Condition Hold Time
From SDA falling edge crossing 30% of VCC
to SCL falling edge crossing 70% of VCC
600
ns
tSU:DAT
Input Data Setup Time
From SDA exiting the 30% to 70% of VCC
window, to SCL rising edge crossing 30% of
VCC
100
ns
tHD:DAT
Input Data Hold Time
From SCL rising edge crossing 70% of VCC
to SDA entering the 30% to 70% of VCC
window
0ns
tSU:STO
STOP Condition Setup Time
From SCL rising edge crossing 70% of VCC,
to SDA rising edge crossing 30% of VCC
600
ns
tHD:STO
STOP Condition Hold Time for Read,
or Volatile Only Write
From SDA rising edge to SCL falling edge;
both crossing 70% of VCC
1300
ns
tDH
Output Data Hold Time
From SCL falling edge crossing 30% of VCC,
until SDA enters the 30% to 70% of VCC
window
0ns
tR
SDA and SCL Rise Time
From 30% to 70% of VCC
20 +
0.1*Cb
250
ns
Operating Specifications Over the recommended operating conditions, unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 21)
TYP
(Note 5)
MAX
(Note 21)
UNIT
ISL22346
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| ISL22346WFV20Z-TK | IC POT DGTL 128TP LN LP 20-TSSOP |
| M83723/84W1831N | CONN RCPT 31POS JAM NUT W/SCKT |
| DS1007S-2/T&R | IC DELAY LINE 4NS 16-SOIC |
| DS1007S-12/T&R | IC DELAY LINE 3NS 16-SOIC |
| VI-B5B-MY-F1 | CONVERTER MOD DC/DC 95V 50W |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| ISL22346WFV20Z | 鍔熻兘鎻忚堪:鏁�(sh霉)瀛楅浕浣嶈▓(j矛) IC 128 TAP FL RNG IND QD DCP 20LD RoHS:鍚� 鍒堕€犲晢:Maxim Integrated 闆婚樆:200 Ohms 婧害绯绘暩(sh霉):35 PPM / C 瀹瑰樊:25 % POT 鏁�(sh霉)閲�:Dual 姣� POT 鍒嗘帴闋�:256 寮у埛瀛樺劜(ch菙)鍣�:Volatile 绶╂矕鍒�: 鏁�(sh霉)瀛楁帴鍙�:Serial (3-Wire, SPI) 鎻忚堪/鍔熻兘:Dual Volatile Low Voltage Linear Taper Digital Potentiometer 宸ヤ綔闆绘簮闆诲:1.7 V to 5.5 V 闆绘簮闆绘祦:27 uA 鏈€澶у伐浣滄韩搴�:+ 125 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:TQFN-16 灏佽:Reel |
| ISL22346WFV20Z-TK | 鍔熻兘鎻忚堪:鏁�(sh霉)瀛楅浕浣嶈▓(j矛) IC 128 TAP FL RNG IND QD DCP 20LD RoHS:鍚� 鍒堕€犲晢:Maxim Integrated 闆婚樆:200 Ohms 婧害绯绘暩(sh霉):35 PPM / C 瀹瑰樊:25 % POT 鏁�(sh霉)閲�:Dual 姣� POT 鍒嗘帴闋�:256 寮у埛瀛樺劜(ch菙)鍣�:Volatile 绶╂矕鍒�: 鏁�(sh霉)瀛楁帴鍙�:Serial (3-Wire, SPI) 鎻忚堪/鍔熻兘:Dual Volatile Low Voltage Linear Taper Digital Potentiometer 宸ヤ綔闆绘簮闆诲:1.7 V to 5.5 V 闆绘簮闆绘祦:27 uA 鏈€澶у伐浣滄韩搴�:+ 125 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:TQFN-16 灏佽:Reel |
| ISL22346WMVEP | 鍒堕€犲晢:Intersil Corporation 鍔熻兘鎻忚堪:DGTL POTENTIOMETER 128POS 10KOHM QUAD 20TSSOP - Rail/Tube |
| ISL22346WMVEP-TK | 鍒堕€犲晢:Intersil Corporation 鍔熻兘鎻忚堪:DGTL POTENTIOMETER 128POS 10KOHM QUAD 20TSSOP - Tape and Reel |
| ISL22349 | 鍒堕€犲晢:INTERSIL 鍒堕€犲晢鍏ㄧū:Intersil Corporation 鍔熻兘鎻忚堪:Quad Digitally Controlled Potentiometers |
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