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參數(shù)資料
| 型號： | ISL22326 |
| 廠商： | Intersil Corporation |
| 英文描述： | Low Noise, Low Power, I2C Bus, 128 Taps(低噪聲,低功率，I2C總線, 128抽頭電位器) |
| 中文描述： | 低噪聲，低功耗，I2C總線，128絲錐（低噪聲，低功率和I2C總線，128抽頭電位器） |
| 文件頁數(shù)： | 5/13頁 |
| 文件大?。?/td> | 488K |
| 代理商： | ISL22326 |
5
FN6176.0
July 17, 2006
EEPROM SPECIFICATION
EEPROM Endurance
1,000,000
Cycles
EEPROM Retention
Temperature
T <55
°
C
50
Years
t
WC
(Note 20)
Non-volatile Write Cycle Time
12
20
ms
SERIAL INTERFACE SPECS
V
IL
A2, A1, A0, SHDN, SDA, and SCL
Input Buffer LOW Voltage
-0.3
0.3*V
CC
V
V
IH
A2, A1, A0, SHDN, SDA, and SCL
Input Buffer HIGH Voltage
0.7*V
CC
V
CC
+0.3
V
Hysteresis
SDA and SCL Input Buffer Hysteresis
0.05*
V
CC
0
V
V
OL
SDA Output Buffer LOW Voltage,
Sinking 4mA
0.4
V
Cpin
(Note 19)
A2, A1, A0, SHDN, SDA, and SCL Pin
Capacitance
10
pF
f
SCL
t
sp
SCL Frequency
400
kHz
Pulse Width Suppression Time at
SDA and SCL Inputs
Any pulse narrower than the max spec is
suppressed
50
ns
t
AA
SCL falling edge to SDA output data
valid
SCL falling edge crossing 30% of V
CC
, until
SDA exits the 30% to 70% of V
CC
window
SDA crossing 70% of V
CC
during a STOP
condition, to SDA crossing 70% of V
CC
during the following START condition
900
ns
t
BUF
Time the Bus Must be Free Before the
Start of a New Transmission
1300
ns
t
LOW
t
HIGH
t
SU:STA
Clock LOW Time
Measured at the 30% of V
CC
crossing
Measured at the 70% of V
CC
crossing
SCL rising edge to SDA falling edge; both
crossing 70% of V
CC
From SDA falling edge crossing 30% of V
CC
to SCL falling edge crossing 70% of V
CC
From SDA exiting the 30% to 70% of V
CC
window, to SCL rising edge crossing 30% of
V
CC
From SCL rising edge crossing 70% of V
CC
to SDA entering the 30% to 70% of V
CC
window
1300
ns
Clock HIGH Time
600
ns
START Condition Setup Time
600
ns
t
HD:STA
START Condition Hold Time
600
ns
t
SU:DAT
Input Data Setup Time
100
ns
t
HD:DAT
Input Data Hold Time
0
ns
t
SU:STO
STOP Condition Setup Time
From SCL rising edge crossing 70% of V
CC
,
to SDA rising edge crossing 30% of V
CC
From SDA rising edge to SCL falling edge;
both crossing 70% of V
CC
From SCL falling edge crossing 30% of V
CC
,
until SDA enters the 30% to 70% of V
CC
window
600
ns
t
HD:STO
STOP Condition Hold Time for Read,
or Volatile Only Write
1300
ns
t
DH
Output Data Hold Time
0
ns
t
R
SDA and SCL Rise Time
From 30% to 70% of V
CC
20 +
0.1 * Cb
250
ns
t
F
SDA and SCL Fall Time
From 70% to 30% of V
CC
20 +
0.1 * Cb
250
ns
Cb
Rpu
Capacitive Loading of SDA or SCL
Total on-chip and off-chip
10
400
pF
SDA and SCL Bus Pull-up Resistor
Off-chip
Maximum is determined by t
R
and t
F
For Cb = 400pF, max is about 2~2.5k
For Cb = 40pF, max is about 15~20k
1
k
Operating Specifications
Over the recommended operating conditions unless otherwise specified.
(Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
(NOTE 5)
MAX
UNIT
ISL22326
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| ISL22326UFR16Z | 功能描述:數(shù)字電位計 IC 128 TAP FL RNG IND DL DCP 16LD 4X4 RoHS:否 制造商:Maxim Integrated 電阻:200 Ohms 溫度系數(shù):35 PPM / C 容差:25 % POT 數(shù)量:Dual 每 POT 分接頭:256 弧刷存儲器:Volatile 緩沖刷: 數(shù)字接口:Serial (3-Wire, SPI) 描述/功能:Dual Volatile Low Voltage Linear Taper Digital Potentiometer 工作電源電壓:1.7 V to 5.5 V 電源電流:27 uA 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFN-16 封裝:Reel |
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