參數(shù)資料
型號(hào)： ISL22319
廠商： Intersil Corporation
英文描述： Low Noise, Low Power, I2C Bus, 128 Taps, Wiper Only(低噪聲,低功率，I2C總線, 128抽頭電位器)
中文描述： 低噪聲，低功耗，I2C總線，128抽頭，雨刷，只有（低噪聲，低功率和I2C總線，128抽頭電位器）
文件頁(yè)數(shù)： 5/13頁(yè)
文件大?。?/td> 384K
代理商： ISL22319
5
FN6310.0
July 3, 2006
NOTES:
5. Typical values are for T
A
= 25°C and 3.3V supply voltage.
6. LSB: [V(R
W
)
127
– V(R
W
)
0
]/127. V(R
W
)
127
and V(R
W
)
0
are V(R
W
) for the DCP register set to 7F hex and 00 hex respectively. LSB is the
incremental voltage when changing from one tap to an adjacent tap.
7. ZS error = V(RW)
0
/LSB.
Hysteresis
SDA and SCL Input Buffer Hysteresis
0.05*
V
CC
V
V
OL
SDA Output Buffer LOW Voltage,
Sinking 4mA
0
0.4
V
Cpin
A1, A0, SHDN, SDA, and SCL Pin
Capacitance
10
pF
f
SCL
t
sp
SCL Frequency
400
kHz
Pulse Width Suppression Time at SDA
and SCL Inputs
Any pulse narrower than the max spec is
suppressed
50
ns
t
AA
SCL Falling Edge to SDA Output Data
Valid
SCL falling edge crossing 30% of V
CC
, until
SDA exits the 30% to 70% of V
CC
window
900
ns
t
BUF
Time the Bus Must be Free before the
Start of a New Transmission
SDA crossing 70% of V
CC
during a STOP
condition, to SDA crossing 70% of V
CC
during the following START condition
1300
ns
t
LOW
Clock LOW Time
Measured at the 30% of V
CC
crossing
1300
ns
t
HIGH
Clock HIGH Time
Measured at the 70% of V
CC
crossing
600
ns
t
SU:STA
START Condition Setup Time
SCL rising edge to SDA falling edge; both
crossing 70% of V
CC
600
ns
t
HD:STA
START Condition Hold Time
From SDA falling edge crossing 30% of V
CC
to SCL falling edge crossing 70% of V
CC
600
ns
t
SU:DAT
Input Data Setup Time
From SDA exiting the 30% to 70% of V
CC
window, to SCL rising edge crossing 30% of
V
CC
100
ns
t
HD:DAT
Input Data Hold Time
From SCL rising edge crossing 70% of V
CC
to SDA entering the 30% to 70% of V
CC
window
0
ns
t
SU:STO
STOP Condition Setup Time
From SCL rising edge crossing 70% of V
CC
,
to SDA rising edge crossing 30% of V
CC
600
ns
t
HD:STO
STOP Condition Hold Time for Read,
or Volatile Only Write
From SDA rising edge to SCL falling edge;
both crossing 70% of V
CC
1300
ns
t
DH
Output Data Hold Time
From SCL falling edge crossing 30% of V
CC
,
until SDA enters the 30% to 70% of V
CC
window
0
ns
t
R
SDA and SCL Rise Time
From 30% to 70% of V
CC
20 +
0.1 * Cb
250
ns
t
F
SDA and SCL Fall Time
From 70% to 30% of V
CC
20 +
0.1 * Cb
250
ns
Cb
Capacitive Loading of SDA or SCL
Total on-chip and off-chip
10
400
pF
Rpu
SDA and SCL Bus Pull-up Resistor
Off-chip
Maximum is determined by t
R
and t
F
For Cb = 400pF, max is about 2~2.5k
Ω
For Cb = 40pF, max is about 15~20k
Ω
1
k
Ω
t
SU:A
A1 and A0 Setup Time
Before START condition
600
ns
t
HD:A
A1 and A0 Hold Time
After STOP condition
600
ns
Operating Specifications
Over the recommended operating conditions unless otherwise specified.
(Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
(NOTE 5)
MAX
UNIT
ISL22319
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