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    參數(shù)資料
    

    


    


    
型號(hào)：
ISL1208IU8Z-T7A

    

    
廠(chǎng)商：
Intersil

    

    
文件頁(yè)數(shù)：
4/24頁(yè)

    

    
文件大小：
0K

    

    
描述：
IC RTC/CALENDAR I2C LP 8MSOP

    

    
標(biāo)準(zhǔn)包裝：
250

    

    
類(lèi)型：
時(shí)鐘/日歷
    		

    

    
特點(diǎn)：
警報(bào)器，閏年，SRAM
    		

    

    
存儲(chǔ)容量：
2B
    		

    

    
時(shí)間格式：
HH:MM:SS（12/24 小時(shí)）
    		

    

    
數(shù)據(jù)格式：
YY-MM-DD-dd
    		

    

    
接口：
I²C，2 線(xiàn)串口
    		

    

    
電源電壓：
2.7 V ~ 5.5 V
    		

    

    
電壓 - 電源，電池：
1.8 V ~ 5.5 V
    		

    

    
工作溫度：
-40°C ~ 85°C
    		

    

    
安裝類(lèi)型：
表面貼裝
    		

    

    
封裝/外殼：
8-TSSOP，8-MSOP（0.118"，3.00mm 寬）
    		

    

    
供應(yīng)商設(shè)備封裝：
8-MSOP
    		

    

    
包裝：
帶卷 (TR)
    		

    

    

    

	
    
    
    

    
    
	
    12
    FN8085.8
    September 12, 2008
    Real Time Clock Registers
    Addresses [00h to 06h]
    RTC REGISTERS (SC, MN, HR, DT, MO, YR, DW)
    These registers depict BCD representations of the time. As
    such, SC (Seconds) and MN (Minutes) range from 0 to 59,
    HR (Hour) can either be a 12-hour or 24-hour mode, DT
    (Date) is 1 to 31, MO (Month) is 1 to 12, YR (Year) is 0 to 99,
    and DW (Day of the Week) is 0 to 6.
    The DW register provides a Day of the Week status and uses
    three bits DW2 to DW0 to represent the seven days of the
    week. The counter advances in the cycle 0-1-2-3-4-5-6-0-1-
    2-… The assignment of a numerical value to a specific day
    of the week is arbitrary and may be decided by the system
    software designer. The default value is defined as “0”.
    24 HOUR TIME
    If the MIL bit of the HR register is “1”, the RTC uses a 24-
    hour format. If the MIL bit is “0”, the RTC uses a 12-hour
    format and HR21 bit functions as an AM/PM indicator with a
    “1” representing PM. The clock defaults to 12-hour format
    time with HR21 = “0”.
    LEAP YEARS
    Leap years add the day February 29 and are defined as those
    years that are divisible by 4. Years divisible by 100 are not leap
    years, unless they are also divisible by 400. This means that
    the year 2000 is a leap year, the year 2100 is not. The ISL1208
    does not correct for the leap year in the year 2100.
    Control and Status Registers
    Addresses [07h to 0Bh]
    The Control and Status Registers consist of the Status
    Register, Interrupt and Alarm Register, Analog Trimming and
    Digital Trimming Registers.
    Status Register (SR)
    The Status Register is located in the memory map at
    address 07h. This is a volatile register that provides either
    control or status of RTC failure, battery mode, alarm trigger,
    write protection of clock counter, crystal oscillator enable and
    auto reset of status bits.
    REAL TIME CLOCK FAIL BIT (RTCF)
    This bit is set to a “1” after a total power failure. This is a read
    only bit that is set by hardware (ISL1208 internally) when the
    device powers up after having lost all power to the device
    (both VDD and VBAT go to 0V). The bit is set regardless of
    whether VDD or VBAT is applied first. The loss of only one of
    the supplies does not set the RTCF bit to “1”. On power-up
    after a total power failure, all registers are set to their default
    states and the clock will not increment until at least one byte
    is written to the clock register. The first valid write to the RTC
    section after a complete power failure resets the RTCF bit to
    “0” (writing one byte is sufficient).
    BATTERY BIT (BAT)
    This bit is set to a “1” when the device enters battery backup
    mode. This bit can be reset either manually by the user or
    automatically reset by enabling the auto-reset bit (see ARST
    bit). A write to this bit in the SR can only set it to “0”, not “1”.
    ALARM BIT (ALM)
    These bits announce if the alarm matches the real time
    clock. If there is a match, the respective bit is set to “1”. This
    bit can be manually reset to “0” by the user or automatically
    reset by enabling the auto-reset bit (see ARST bit). A write to
    this bit in the SR can only set it to “0”, not “1”.
    NOTE: An alarm bit that is set by an alarm occurring during an SR
    read operation will remain set after the read operation is complete.
    WRITE RTC ENABLE BIT (WRTC)
    The WRTC bit enables or disables write capability into the
    RTC Timing Registers. The factory default setting of this bit
    is “0”. Upon initialization or power-up, the WRTC must be set
    to “1” to enable the RTC. Upon the completion of a valid
    write (STOP), the RTC starts counting. The RTC internal
    1Hz signal is synchronized to the STOP condition during a
    valid write cycle.
    CRYSTAL OSCILLATOR ENABLE BIT (XTOSCB)
    This bit enables/disables the internal crystal oscillator. When
    the XTOSCB is set to “1”, the oscillator is disabled, and the
    X1 pin allows for an external 32kHz signal to drive the RTC.
    The XTOSCB bit is set to “0” on power-up.
    AUTO RESET ENABLE BIT (ARST)
    This bit enables/disables the automatic reset of the BAT and
    ALM status bits only. When ARST bit is set to “1”, these
    status bits are reset to “0” after a valid read of the respective
    status register (with a valid STOP condition). When the
    ARST is cleared to “0”, the user must manually reset the
    BAT and ALM bits.
    Interrupt Control Register (INT)
    TABLE 2. STATUS REGISTER (SR)
    ADDR
    7
    6
    5
    4
    3
    2
    1
    0
    07h
    ARST XTOSCB reserved WRTC reserved ALM BAT RTCF
    Default
    0
    000
    0
    TABLE 3. INTERRUPT CONTROL REGISTER (INT)
    ADDR
    7
    6
    5
    4
    3210
    08h
    IM
    ALME
    LPMODE FOBATB FO3 FO2 FO1 FO0
    Default
    0
    0000
    ISL1208
    
    
    
    
    
    


    


    

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