參數(shù)資料
型號(hào): ISL12030IBZ
廠商: Intersil
文件頁(yè)數(shù): 3/17頁(yè)
文件大?。?/td> 0K
描述: IC RTC/CALENDAR EEPROM 8-SOIC
產(chǎn)品培訓(xùn)模塊: Solutions for Industrial Control Applications
標(biāo)準(zhǔn)包裝: 980
類型: 時(shí)鐘/日歷
特點(diǎn): 警報(bào)器,夏令時(shí),SRAM
存儲(chǔ)容量: 128B
時(shí)間格式: HH:MM:SS:hh(12/24 小時(shí))
數(shù)據(jù)格式: YY-MM-DD-dd
接口: I²C,2 線串口
電源電壓: 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 管件
11
FN6617.2
May 5, 2011
ALARM Registers (1Dh to 28h)
The alarm register bytes are set up identical to the RTC
register bytes, except that the MSB of each byte functions as
an enable bit (enable = “1”). These enable bits specify which
alarm registers (seconds, minutes, etc.) are used to make
the comparison. Note that there is no alarm byte for year.
The alarm function works as a comparison between the
alarm registers and the RTC registers. As the RTC
advances, the alarm will be triggered once a match occurs
between the alarm registers and the RTC registers. Any one
alarm register, multiple registers, or all registers can be
enabled for a match.
There are two alarm operation modes: Single Event and
periodic Interrupt Mode.
Single Event Mode is enabled by setting either ALE0 or
ALE1 to 1, then setting bit 7 on any of the Alarm registers
(ESCA... EDWA) to “1”, and setting the IM bit to “0”. This
mode permits a one-time match between the Alarm registers
and the RTC registers. Once this match occurs, the ALM bit
is set to “1” and the IRQ output will be pulled LOW and will
remain LOW until the ALM bit is reset. This can be done
manually or by using the auto-reset feature. Since the IRQ
output is shared by both alarms, they both need to be reset
in order for the IRQ output to go HIGH.
Interrupt Mode is enabled by setting either ALE0 or ALE1 to
1, then setting bit 7 on any of the Alarm registers (ESCA...
EDWA) to “1”, and setting the IM bit to “1”. Setting the IM bit
to 1 puts both ALM0 and ALM1 into Interrupt mode. The IRQ
output will now be pulsed each time an alarm occurs (either
AL0 or AL1). This means that once the interrupt mode alarm
is set, it will continue to alarm until it is reset.
To clear a single event alarm, the corresponding ALM0 or
ALM1 bit in the SRDC register must be set to “0” with a write.
Note that if the ARST bit is set to “1” (address 0Ch, bit 7), the
ALM0 and ALM1 bits will automatically be cleared when the
status register is read.
The IRQ output will be set by an alarm match for either
ALM0 or ALM1.
Following are examples of both Single Event and periodic
Interrupt Mode alarms.
Example 1
Alarm set with single interrupt (IM = ”0”)
A single alarm will occur on January 1 at 11:30am
Set Alarm registers as follows:
After these registers are set, an alarm will be generated when
the RTC advances to exactly 11:30 a.m. on January 1 (after
seconds changes from 59 to 00) by setting the ALM0 bit in the
status register to “1” and also bringing the IRQ output LOW.
TABLE 5. DST FORWARD REGISTERS
ADDRESS
FUNCTION
7
6
5
4
3
2
1
0
15h
Month Forward
DSTE
0
MoFd20
MoFd13
MoFd12
MoFd11
MoFd10
16h
Day Forward
0
DwFdE
WkFd12
WkFd11
WkFd10
DwFd12
DwFd11
DwFd10
17h
Date Forward
0
DtFd21
DtFd20
DtFd13
DtFd12
DtFd11
DtFd10
18h
Hour Forward
HrFdMIL
0
HrFd21
HrFd20
HrFd13
HrFd12
HrFd11
HrFd10
TABLE 6. DST REVERSE REGISTERS
ADDRESS
NAME
7
6
5
4
3
2
1
0
19h
Month Reverse
0
MoRv20
MoRv13
MoRv12
MoRv11
MoRv10
1Ah
Day Reverse
0
DwRvE
WkRv12
WkRv11
WkRv10
DwRv12
DwRv11
DwRv10
1Bh
Date Reverse
0
DtRv21
DtRv20
DtRv13
DtRv12
DtRv11
DtRv10
1Ch
Hour Reverse
HrRvMIL
0
HrRv21
HrRv20
HrRv13
HrRv12
HrRv11
HrRv10
ALARM
REGISTER
BIT
DESCRIPTION
7
6543210
HEX
SCA0
0
0000000
00h
Seconds disabled
MNA0
1
0110000
B0h
Minutes set to 30,
enabled
HRA0
1
0010001
91h
Hours set to 11,
enabled
DTA0
1
0000001
81h
Date set to 1,
enabled
MOA0
1
0000001
81h
Month set to 1,
enabled
DWA0
0
0000000
00h
Day of week
disabled
ISL12030
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