tHIGH Clock HIGH Time Measured at the 70% of V
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寤犲晢锛� Intersil
鏂囦欢闋佹暩(sh霉)锛� 26/29闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC RTC EEPROM LP 4.38V 14-SOIC
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椤炲瀷锛� 鏅傞悩/鏃ユ
鐗归粸锛� 璀﹀牨鍣�锛岄枏骞�锛岀洠(ji膩n)鎺у櫒锛岀洠(ji膩n)瑕栬▓鏅傚櫒
鏅傞枔鏍煎紡锛� HH:MM:SS锛�12/24 灏忔檪锛�
鏁�(sh霉)鎿�(j霉)鏍煎紡锛� YY-MM-DD-dd
鎺ュ彛锛� I²C锛�2 绶氫覆鍙�
闆绘簮闆诲锛� 2.7 V ~ 5.5 V
闆诲 - 闆绘簮锛岄浕姹狅細 1.8 V ~ 5.5 V
宸ヤ綔婧害锛� -40°C ~ 85°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 14-SOIC锛�0.154"锛�3.90mm 瀵級
渚涙噳鍟嗚ō鍌欏皝瑁濓細 14-SOICN
鍖呰锛� 鍓垏甯� (CT)
鍏跺畠鍚嶇ū锛� ISL12029IBZ-TCT
6
FN6206.10
December 16, 2010
tHIGH
Clock HIGH Time
Measured at the 70% of VDD
crossing.
600
ns
tSU:STA
START Condition Setup Time
SCL rising edge to SDA falling
edge. Both crossing 70% of VDD.
600
ns
tHD:STA
START Condition Hold Time
From SDA falling edge crossing
30% of VDD to SCL falling edge
crossing 70% of VDD.
600
ns
tSU:DAT
Input Data Setup Time
From SDA exiting the 30% to
70% of VDD window, to SCL rising
edge crossing 30% of VDD
100
ns
tHD:DAT
Input Data Hold Time
From SCL falling edge crossing
70% of VDD to SDA entering the
30% to 70% of VDD window.
0
ns
tSU:STO
STOP Condition Setup Time
From SCL rising edge crossing
70% of VDD, to SDA rising edge
crossing 30% of VDD.
600
ns
tHD:STO
STOP Condition Hold Time for
Read, or Volatile Only Write
From SDA rising edge to SCL
falling edge. Both crossing 70%
of VDD.
600
ns
tDH
Output Data Hold Time
From SCL falling edge crossing
30% of VDD, until SDA enters the
30% to 70% of VDD window.
0
ns
Cpin
SDA, and SCL Pin Capacitance
10
pF
tWC
Non-Volatile Write Cycle Time
12
20
ms
tR
SDA and SCL Rise Time
From 30% to 70% of VDD
20 +
0.1xCb
250
ns
tF
SDA and SCL Fall Time
From 70% to 30% of VDD
20 +
0.1 x Cb
250
ns
Cb
Capacitive Loading of SDA or SCL Total on-chip and off-chip
10
400
pF
Rpu
SDA and SCL Bus Pull-up Resistor
Off-chip
Maximum is determined by tR and
tF.
For Cb = 400pF, max is about
2k
惟~2.5k惟.
For Cb = 40pF, max is about
15k
惟~20k惟
1
k
惟
NOTES:
7. IRQ/FOUT Inactive (no frequency output and no alarms).
8. VIL = VDD x 0.1, VIH = VDD x 0.9, fSCL = 400kHz.
9. VRESET = 2.63V (VDD must be greater than VRESET), VBAT = 0V.
10. Bit BSW = 0 (Standard Mode), ATR = 00h, VBAT 鈮� 1.8V.
11. Specified at +25掳C.
12. In order to ensure proper timekeeping, the VDD SR- specification must be followed.
13. Parameter is not 100% tested.
14. tWC is the minimum cycle time to be allowed for any non-volatile Write by the user, it is the time from valid STOP condition at the end of Write
sequence of a serial interface Write operation, to the end of the self-timed internal non-volatile write cycle.
15. These are I2C specific parameters and are not directly tested, however they are used during device testing to validate device specification.
16. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
Serial Interface (I2C) Specifications - DC/AC Characteristics (Continued)
SYMBOL
PARAMETER
CONDITIONS
MIN
(Note 16)
TYP
MAX
(Note 16)
UNITS
NOTES
ISL12029, ISL12029A
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