參數(shù)資料
型號: ISL12025IBZ
廠商: Intersil
文件頁數(shù): 11/27頁
文件大?。?/td> 0K
描述: IC RTC/CALENDAR EEPROM 8-SOIC
標準包裝: 98
類型: 時鐘/日歷
特點: 警報器,閏年,監(jiān)控器,唯一 ID,監(jiān)視計時器
時間格式: HH:MM:SS(12/24 小時)
數(shù)據(jù)格式: YY-MM-DD-dd
接口: I²C,2 線串口
電源電壓: 2.7 V ~ 5.5 V
電壓 - 電源,電池: 1.8 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應商設備封裝: 8-SOIC
包裝: 管件
產(chǎn)品目錄頁面: 1245 (CN2011-ZH PDF)
19
FN6371.3
August 13, 2008
Acknowledge Polling
Disabling of the inputs during non-volatile write cycles can
be used to take advantage of the typical 5ms write cycle
time. Once the stop condition is issued to indicate the end of
the master’s byte load operation, the ISL12025 initiates the
internal non-volatile write cycle. Acknowledge polling can
begin immediately. To do this, the master issues a start
condition followed by the Memory Array Slave Address Byte
for a write or read operation (AEh or AFh). If the ISL12025 is
still busy with the non-volatile write cycle, then no ACK will
be returned. When the ISL12025 has completed the write
operation, an ACK is returned and the host can proceed with
the read or write operation. See the flow chart in
Figure 24. Note: Do not use the CCR Slave byte (DEh or
DFh) for Acknowledge Polling.
Read Operations
There are three basic read operations: Current Address
Read, Random Read and Sequential Read.
Current Address Read
Internally the ISL12025 contains an address counter that
maintains the address of the last word read incremented by
one. Therefore, if the last read was to address n, the next
read operation would access data from address n + 1. On
power-up, the 16-bit address is initialized to 0h. In this way, a
current address read immediately after the power-on reset
can download the entire contents of memory starting at the
first location. Upon receipt of the Slave Address Byte with
the R/W bit set to one, the ISL12025 issues an
acknowledge, then transmits eight data bits. The master
terminates the read operation by not responding with an
acknowledge during the ninth clock and issuing a stop
condition. See Figure 23 for the address, acknowledge, and
data transfer sequence.
S
T
A
R
T
S
T
O
P
SLAVE
ADDRESS
WORD
ADDRESS 1
DATA
A
C
K
A
C
K
A
C
K
SDA BUS
SIGNALS FROM
THE SLAVE
SIGNALS FROM
THE MASTER
0
A
C
K
WORD
ADDRESS 0
1
00 0 0 0 0 0
FIGURE 20. BYTE WRITE SEQUENCE
ADDRESS
10
6 BYTES
15
6 BYTES
ADDRESS = 5
ADDRESS POINTER ENDS
FIGURE 21. WRITING 12 BYTES TO A 16-BYTE MEMORY PAGE STARTING AT ADDRESS 10
AT ADDR = 5
WORD
ADDRESS 0
S
T
A
R
T
S
T
O
P
SLAVE
ADDRESS
WORD
ADDRESS 1
DATA
(n)
A
C
K
A
C
K
A
C
K
SDA BUS
SIGNALS FROM
THE SLAVE
SIGNALS FROM
THE MASTER
0
DATA
(1)
A
C
K
1
n 16 FOR EEPROM ARRAY
1
n 8 FOR CCR
1
0 0 00 00 0
FIGURE 22. PAGE WRITE SEQUENCE
ISL12025
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