21 FN6659.3 November 22, 2011 Time Stamp VDD to Battery Registers (TSV2" />
參數(shù)資料
型號： ISL12022IBZ-T7A
廠商： Intersil
文件頁數(shù)： 14/29頁
文件大?。?/td> 0K
描述： IC RTC/CALENDAR TEMP SNSR 8SOIC
應(yīng)用說明： Addressing Power Issues in Real Time Clock Appls
產(chǎn)品培訓(xùn)模塊： Solutions for Industrial Control Applications
標(biāo)準(zhǔn)包裝： 250
類型： 時鐘/日歷
特點(diǎn)： 警報器，夏令時，閏年，SRAM
存儲容量： 128B
時間格式： HH:MM:SS（12/24 小時）
數(shù)據(jù)格式： YY-MM-DD-dd
接口： I²C，2 線串口
電源電壓： 2.7 V ~ 5.5 V
電壓 - 電源，電池： 1.8 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 8-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 8-SOIC
包裝： 帶卷 (TR)
ISL12022
21
FN6659.3
November 22, 2011
Time Stamp VDD to Battery Registers (TSV2B)
The TSV2B Register bytes are identical to the RTC register bytes,
except they do not extend beyond the Month. The Time Stamp
captures the FIRST VDD to Battery Voltage transition time, and will
not update upon subsequent events, until cleared (only the first
event is captured before clearing). Set CLRTS = 1 to clear this
register (Add 09h, PWR_VDD register).
Note that the time stamp registers are cleared to all “0”,
including the month and day, which is different from the RTC and
alarm registers (those registers default to 01h). This is the
indicator that no time stamping has occurred since the last clear
or initial power-up. Once a time stamp occurs, there will be a non-
zero time stamp.
Time Stamp Battery to VDD Registers (TSB2V)
The Time Stamp Battery to VDD Register bytes are identical to
the RTC register bytes, except they do not extend beyond Month.
The Time Stamp captures the LAST transition of VBAT to VD (only
the last event of a series of power-up/down events is retained).
Set CLRTS = 1 to clear this register (Add 09h, PWR_VDD register).
DST Control Registers (DSTCR)
8 bytes of control registers have been assigned for the Daylight
Savings Time (DST) functions. DST beginning (set Forward) time
is controlled by the registers DstMoFd, DstDwFd, DstDtFd, and
DstHrFd. DST ending time (set Backward or Reverse) is controlled
by DstMoRv, DstDwRv, DstDtRv and DstHrRv.
Tables 20 and 21 describe the structure and functions of the DSTCR.
DST FORWARD REGISTERS (20H TO 23H)
DST forward is controlled by the following DST Registers:
DST Enable
DSTE is the DST Enabling Bit located in Bit 7 of register 20h
(DstMoFdxx). Set DSTE = 1 will enable the DSTE function. Upon
powering up for the first time (including battery), the DSTE bit
defaults to “0”. When DSTE is set to “1” the RTC time must be at
least one hour before the scheduled DST time change for the
correction to take place. When DSTE is set to “0”, the DSTADJ bit
in the Status Register automatically resets to “0”.
DST Month Forward
DstMoFd sets the Month that DST starts. The format is the same
as for the RTC register month, from 1 to 12. The default value for
the DST begin month is 00h.
TABLE 20. DST FORWARD REGISTERS
ADDRESS
FUNCTION
7
6
5
4
321
0
20h
Month Forward
DSTE
0
MoFd20
MoFd13
MoFd12
MoFd11
MoFd10
21h
Day Forward
0
DwFdE
WkFd12
WkFd11
WkFd10
DwFd12
DwFd11
DwFd10
22h
Date Forward
0
DtFd21
DtFd20
DtFd13
DtFd12
DtFd11
DtFd10
23h
Hour Forward
0
HrFd21
HrFd20
HrFd13
HrFd12
HrFd11
HrFd10
TABLE 21. DST REVERSE REGISTERS
ADDRESS
NAME
7
654
321
0
24h
Month Reverse
0
MoRv20MoRv13
MoRv12MoRv11MoRv10
25h
Day Reverse
0
DwRvE
WkRv12
WkRv11
WkRv10
DwRv12
DwRv11
DwRv10
26h
Date Reverse
0
DtRv21
DtRv20
DtRv13
DtRv12
DtRv11
DtRv10
27h
Hour Reverse
0
HrRv21
HrRv20
HrRv13
HrRv12
HrRv11
HrRv10
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