參數(shù)資料
型號: ISD5116SI
廠商: WINBOND ELECTRONICS CORP
元件分類: 音頻合成
英文描述: Single-Chip Voice Record/Playback Device Up to 16-Minute Duration with Digital Storage Capability
中文描述: 960 SEC, SPEECH SYNTHESIZER WITH RCDG, PDSO28
封裝: 0.300 INCH, PLASTIC, SOIC-28
文件頁數(shù): 45/57頁
文件大?。?/td> 735K
代理商: ISD5116SI
October 2000
Page 44
I
2
C Interface Timing
STANDARD-MODE
SYMBOL
MIN.
f
SCL
0
t
HD; STA
4.0
FAST-MODE
PARAMETER
MAX.
100
-
MIN.
0
0.6
MAX.
400
-
UNIT
SCL clock frequency
Hold time (repeated) START
condition. After this period, the first
clock pulse is generated
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START
condition
Data set-up time
Rise time of both SDA and SCL
signals
Fall time of both SDA and SCL
signals
Set-up time for STOP condition
Bus-free time between a STOP and
START condition
Capacitive load for each bus line
Noise margin at the LOW level for
each connected device (including
hysteresis)
Noise margin at the HIGH level for
each connected device (including
hysteresis)
kHz
μ
s
t
LOW
t
HIGH
t
SU; STA
4.7
4.0
4.7
-
-
-
1.3
0.6
0.6
-
-
-
μ
s
μ
s
μ
s
t
SU; DAT
t
r
250
-
-
100
(1)
-
ns
ns
1000
20 + 0.1C
b
(2)
300
t
f
-
300
20 + 0.1C
b
(2)
300
ns
t
SU; STO
t
BUF
4.0
4.7
-
-
0.6
1.3
-
-
μ
s
μ
s
C
b
V
nL
-
400
-
-
400
-
pF
V
0.1 V
DD
0.1 V
DD
V
nH
0.2 V
DD
-
0.2 V
DD
-
V
1. A Fast-mode I
2
C-interface device can be used in a Standard-mode I
2
C-interface system, but the requirement
t
SU;DAT
> 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW
period of the SCL signal.
If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line;
t
r max
+ t
SU;DAT
= 1000 + 250 = 1250 ns (according to the Standard-mode I
2
C -interface specification) before the
SCL line is released.
2. C
b
= total capacitance of one bus line in pF. If mixed with HS mode devices, faster fall-times are allowed.
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