參數(shù)資料
型號(hào)： IS80C88-2
廠商： INTERSIL CORP
元件分類： 微控制器/微處理器
英文描述： CMOS 8/16-Bit Microprocessor
中文描述： 16-BIT, 8 MHz, MICROPROCESSOR, PQCC44
封裝： PLASTIC, LCC-44
文件頁(yè)數(shù)： 24/32頁(yè)
文件大小： 246K
代理商： IS80C88-2
3-24
FIGURE 26. REQUEST/GRANT SEQUENCE TIMING (MAXIMUM MODE ONLY)
NOTE: The coprocessor may not drive the busses outside the region shown without risking contention.
FIGURE 27. HOLD/HOLD ACKNOWLEDGE TIMING (MINIMUM MODE ONLY)
NOTE: Setup requirements for asynchronous signals only to guarantee recognition at next CLK.
FIGURE 28. ASYNCHRONOUS SIGNAL RECOGNITION
NOTE: Setup requirements for asynchronous signals only to guar-
antee recognition at next CLK.
FIGURE 29. BUS LOCK SIGNAL TIMING (MAXIMUM MODE
ONLY)
Waveforms
(Continued)
CLK
TCLGH
RQ/GT
PREVIOUS GRANT
AD7-AD0
RD, LOCK
A19/S6-A16/S3
S2, S1, S0
TCLCL
ANY
CLK
CYCLE
> 0-CLK
CYCLES
PULSE 2
80C88 GT
80C88
TGVCH (14)
TCHGX (15)
TCLGH (44)
PULSE 1
COPROCESSOR
RQ
TCLAZ (25)
PULSE 3
COPROCESSOR
RELEASE
(SEE NOTE)
TCHSZ (26)
(1)
TCLGL
(43)
COPROCESSOR
TCHSV (21)
(44)
CLK
HOLD
HLDA
A15-A8
A19/S6-A16/S3
RD, WR, I/O/M, DT/R, DEN, SSO
80C88
THVCH (13)
(SEE NOTE)
TCLHAV (36)
≥
1CLK
CYCLE
1 OR 2
CYCLES
TCLAZ (19)
COPROCESSOR
80C88
TCLHAV (36)
TCHSZ (20)
THVCH (13)
TCHSV (21)
AD7-AD0
NMI
INTR
TEST
CLK
SIGNAL
TINVCH (SEE NOTE)
(13)
ANY CLK CYCLE
CLK
LOCK
TCLAV
(23)
ANY CLK CYCLE
TCLAV
(23)
80C88
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