
Integrated Silicon Solution, Inc. — www.issi.com
1
Rev. D
09/10/07
Copyright 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
IS61NLP12832B
IS61NLP12836B/IS61NVP12836B
IS61NLP25618A/IS61NVP25618A
FEATURES
100percentbusutilization
NowaitcyclesbetweenReadandWrite
Internalself-timedwritecycle
IndividualByteWriteControl
SingleR/W(Read/Write)controlpin
Clockcontrolled,registeredaddress,
data and control
Interleavedorlinearburstsequencecontrolus-
ing MODE input
Threechipenablesforsimpledepthexpansion
and address pipelining
PowerDownmode
Commondatainputsanddataoutputs
CKE pin to enable clock and suspend operation
JEDEC100-pinTQFP,165-ballPBGAand119-
ballPBGApackages
Powersupply:
NVP:Vdd 2.5V(±5%),Vddq2.5V(±5%)
NLP:Vdd3.3V(±5%),Vddq3.3V/2.5V(±5%)
Industrialtemperatureavailable
Lead-freeavailable
DESCRIPTION
The4Meg'NLP/NVP'productfamilyfeaturehigh-speed,
low-powersynchronousstaticRAMsdesignedtoprovide
aburstable,high-performance,'nowait'state,devicefor
networking and communications applications.They are
organizedas128Kwordsby32bits,128Kwordsby36
bits,and256Kwordsby18bits,fabricatedwith
ISSI's
advanced CMOS technology.
Incorporating a 'no wait' state feature, wait cycles are
eliminated when the bus switches from read to write, or
writetoread.Thisdeviceintegratesa2-bitburstcounter,
high-speedSRAMcore,andhigh-drivecapabilityoutputs
into a single monolithic circuit.
All synchronous inputs pass through registers are controlled
byapositive-edge-triggeredsingleclockinput.Operations
may be suspended and all synchronous inputs ignored
when Clock Enable, CKEisHIGH.Inthisstatetheinternal
device will hold their previous values.
AllRead,WriteandDeselectcyclesareinitiatedbytheADV
input.WhentheADVisHIGHtheinternalburstcounter
isincremented.Newexternaladdressescanbeloaded
whenADVisLOW.
Write cycles are internally self-timed and are initiated
by the rising edge of the clock inputs and when WE is
LOW.Separatebyteenablesallowindividualbytestobe
written.
Aburstmodepin(MODE)definestheorderoftheburst
sequence.WhentiedHIGH,theinterleavedburstsequence
isselected.WhentiedLOW,thelinearburstsequenceis
selected.
128K x 32, 128K x 36, and 256K x 18
4Mb, PIPELINE 'NO WAIT' STATE BUS SRAM
SEPTEMBER 2007
FAST ACCESS TIME
Symbol
Parameter
-250
-200
Units
tkq
ClockAccessTime
2.6
3.1
ns
tkc
CycleTime
4
5
ns
Frequency
250
200
MHz