參數(shù)資料
型號(hào): IS61C64AH-25U
英文描述: 8K x 8 HIGH-SPEED CMOS STATIC RAM
中文描述: 8K的× 8高速CMOS靜態(tài)RAM
文件頁(yè)數(shù): 6/8頁(yè)
文件大?。?/td> 433K
代理商: IS61C64AH-25U
IS61C64AH
6
Integrated Circuit Solution Inc.
SR001-B
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,3)
(Over Operating Range)
-12 ns
-15 ns
-20 ns
-25 ns
Min.
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Max.
Unit
t
WC
Write Cycle Time
12
15
20
25
ns
t
SCE
1
CE1
to Write End
10
12
17
22
ns
t
SCE
2
CE2 to Write End
10
12
17
22
ns
t
AW
Address Setup Time to Write End
10
12
15
20
ns
t
HA
Address Hold from Write End
0
0
0
0
ns
t
SA
Address Setup Time
0
0
0
0
ns
t
PWE
(4)
WE
Pulse Width
8
10
12
15
ns
t
SD
Data Setup to Write End
8
9
10
12
ns
t
HD
Data Hold from Write End
0
0
0
0
ns
t
HZWE
(2)
WE
LOW to High-Z Output
6
8
10
12
ns
t
LZWE
(2)
WE
HIGH to Low-Z Output
0
0
0
0
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of
CE1
LOW, CE2 HIGH and
WE
LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
AC WAVEFORMS
WRITE CYCLE NO. 1
(
CE
Controlled,
OE
is HIGH or LOW)
(1 )
DATA UNDEFINED
t
WC
VALID ADDRESS
t
SCE1
t
SCE2
t
PWE1
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE1
CE2
WE
D
OUT
D
IN
DATA
IN
VALID
t
LZWE
t
SD
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