參數(shù)資料
型號(hào)： IS43R32800B-5BL
廠商： INTEGRATED SILICON SOLUTION INC
元件分類(lèi)： DRAM
英文描述： 8M X 32 DDR DRAM, 0.7 ns, PBGA144
封裝： 12 X 12 MM, 0.80 MM PITCH, LEAD FREE, MINI, FBGA-144
文件頁(yè)數(shù)： 13/39頁(yè)
文件大?。?/td> 507K
代理商： IS43R32800B-5BL
20
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00D
03/19/08
IS43R32800B
Burst Length
Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable, as
shown in Figure “CAS LATENCY”. The burst length determines the maximum number of column locations that can
be accessed for a given READ or WRITE command. Burst lengths of 2, 4, or 8 locations are available for both the
sequential and the interleaved burst types.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When
a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is
reached. The block is uniquely selected by A1--Ai when the burst length is set to two, by A2--Ai when the burst
length is set to four and by A3--Ai when the burst length is set to eight (where Ai is the most significant column
address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the
starting location within the block. The programmed burst length applies to both read and write bursts.
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this
is referred to as the burst type and is selected via bit A3. The ordering of accesses within a burst is determined by
the burst length, the burst type and the starting column address, as shown in Table “BURST DEFINITION”.
Read Latency
The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of
the first piece of output data. If a READ command is registered at clock edge n, and the latency is m clocks, the
data will be available nominally coincident with clock edge n + m.
Reserved states should not be used as unknown operation, or incompatibility with future versions may result.
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參數(shù)描述
IS43R32800B-5BLI 功能描述:動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器 256Mb (16M x 16) DDR, 2.5v, 200MHz RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲(chǔ)容量:16 MB 最大時(shí)鐘頻率: 訪問(wèn)時(shí)間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube
IS43R32800B-5BLI-TR 功能描述:動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器 256Mb (16M x 16) DDR, 2.5v, 200MHz RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲(chǔ)容量:16 MB 最大時(shí)鐘頻率: 訪問(wèn)時(shí)間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube
IS43R32800B-5BL-TR 功能描述:動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器 256M (16Mx16) 400MHz DDR 2.5v RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲(chǔ)容量:16 MB 最大時(shí)鐘頻率: 訪問(wèn)時(shí)間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube
IS43R32800B-5B-TR 功能描述:動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器 256M (16Mx16) 400MHz Commercial Temp RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲(chǔ)容量:16 MB 最大時(shí)鐘頻率: 訪問(wèn)時(shí)間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube
IS43R32800B-6B 功能描述:動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器 256M (16Mx16) 333MHz Commercial Temp RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲(chǔ)容量:16 MB 最大時(shí)鐘頻率: 訪問(wèn)時(shí)間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube
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