參數(shù)資料
型號: IRU3146CF
廠商: International Rectifier
英文描述: DUAL SYNCHRONOUS PWM CONTROLLER WITH CURRENT SHARING CIRCUITRY AND AUTO-RESTART
中文描述: 雙同步PWM控制器,帶有均流電路和自動重新啟動
文件頁數(shù): 4/30頁
文件大?。?/td> 528K
代理商: IRU3146CF
4
Rev. 1.1
6/25/04
IRU3146
www.irf.com
PIN DESCRIPTIONS
PIN# PIN SYMBOL
1
2
3
4
5,23
6,22
Fb2,Fb1
PIN DESCRIPTION
Power Good pin. Low when any of the outputs fall 10% below the set voltages.
Supply voltage for the internal blocks of the IC.
Output of the internal LDO.
Switching frequency setting resistor. (see Figure 10 for selecting resistor values).
Sense pins for OVP and PGood. For 2-Phase operation tie these pins together.
Inverting inputs to the error amplifiers. In current sharing mode, Fb1 is connected to a
resistor divider to set the output voltage and Fb2 is connected to programming resistor to
achieve current sharing. In independent 2-channel mode, these pins work as feedback
inputs for each channel.
Compensation pins for the error amplifiers.
These pins provide soft-start for the switching regulator. An internal current source charges
external capacitors that are connected from these pins to ground which ramp up the
output of the switching regulators, preventing them from overshooting as well as limiting
the input current. The converter can be shutdown by pulling these pins below 0.3V.
Current limit resistor (R
LIM
) connection pins for output 1 and 2. The other ends of R
LIM
s are
connected to the corresponding switching nodes.
Supply voltage for the high side output drivers. These are connected to voltages that must
be typically 6V higher than their bus voltages. A 1
μ
F high frequency capacitor must be
connected from these pins to GND to provide peak drive current capability.
Output drivers for the high side power MOSFETs.
1)
These pins serve as the separate grounds for MOSFET drivers and should be connected
to the system’s ground plane.
Output drivers for the synchronous power MOSFETs.
Supply voltage for the low side output drivers. This pin should be high for normal operation
The internal oscillator may be synchronized to an external clock via this pin.
When pulled High, it puts the device current limit into a hiccup mode. When pulled Low,
the output latches off, after an overcurrent event.
7,21
8
20
9,19
10,18
11,17
12,16
13,15
14
24
25
PGood
Vcc
V
OUT3
Rt
V
SEN2
, V
SEN1
Comp2, Comp1
SS2 / SD
SS1 / SD
OCSet2,OCSet1
VcH2, VcH1
HDrv2, HDrv1
PGnd2, PGnd1
LDrv2, LDrv1
V
CL
Sync
Hiccup
Figure 2 - Deadband time definition.
T
DB(TYP)
=(Deadband H_toL+Deadband L_to -H)/2
DEADBAND TIME
90%
10%
90%
10%
High Side
Driver HD
Low Side
Driver LD
Tr
Tf
Deadband
H_to_L
Deadband
L_to_H
Tr
Tf
2V
2V
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