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參數(shù)資料
| 型號(hào)： | IRP2166 |
| 廠商： | International Rectifier |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | PFC & BALLAST CONTROL IC |
| 中文描述： | 功率因數(shù)校正 |
| 文件頁數(shù)： | 24/32頁 |
| 文件大?。?/td> | 616K |
| 代理商： | IRP2166 |
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IR2166 & (PbF)
24
www.irf.com
RVBUS1
RVBUS
CCOMP
LPFC
MPFC
RPFC
DFPC
CBUS
(+)
(-)
RZX
PFC
Control
VBUS
COMP
PFC
ZX
COM
DCOMP
Figure 8:IR2166 simplified PFC control circuit
The VBUS pin is regulated against a fixed
internal 4V reference voltage for regulating the
DC bus voltage (Figure 9). The feedback loop
is performed by an operational transconductance
amplifier (OTA) that sinks or sources a current
to the external capacitor at the COMP pin. The
resulting voltage on the COMP pin sets the
threshold for the charging of the internal timing
capacitor (C1) and therefore programs the on-
time of MPFC. During preheat and ignition
modes of the ballast section, the gain of the
OTA is set to a high level to raise the DC bus
level quickly. When the voltage on the V
BUS
pin
exceeds 3V, the gain is set to a low level to
reduce overshoot. When the voltage on the V
BUS
pin exceeds 4V, the gain is set to a high level
again to minimize the transient on the DC bus
which can occur during ignition. During run
mode, the gain is then decreased to a lower
level necessary for achieving high power factor
and low THD.
Figure 9: IR2166 detailed PFC control circuit
The off-time of MPFC is determined by the time
it takes the LPFC current to discharge to zero.
This zero current level is detected by a
secondary winding on LPFC which is connected
to the ZX pin. A positive-going edge exceeding
the internal 2V threshold signals the beginning
of the off-time. A negative-going edge on the
ZX pin falling below 1.7V will occur when the
LPFC current discharges to zero which signals
the end of the off-time and MPFC is turned on
again (Figure 10). The cycle repeats itself
indefinitely until the PFC section is disabled due
to a fault detected by the ballast section (Fault
Mode), an over-voltage or under-voltage
condition on the DC bus, or, the negative
transition of ZX pin voltage does not occur.
Should the negative edge on the ZX pin not occur,
MPFC will remain off until the watch-dog timer
forces a turn-on of MPFC for an on-time duration
programmed by the voltage on the COMP pin.
The watch-dog pulses occur every 400
μ
s
indefinitely until a correct positive- and negative-
going signal is detected on the ZX pin and normal
PFC operation is resumed.
7
6
1
Q
S
R
Q
2.0V
VBUS
COMP
ZX
7.6V
4.0V
GAIN
OTA1
4.3V
8
PFC
Q
S
R1
R2 Q
COMP3
COMP4
COMP5
RS3
RS4
VCC
Run Mode Signal
Fault Mode Signal
M1
WATCH
DOG
TIMER
M2
C1
3.0V
Discharge
VCC to
UVLO-
COMP2
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