參數(shù)資料
型號(hào)： IRLSG5653
廠商： International Rectifier
英文描述： INTEGRATED SWITCHER
中文描述： 多功能開關(guān)
文件頁數(shù)： 3/7頁
文件大?。?/td> 271K
代理商： IRLSG5653
www.irf.com
Electrical Characteristics (for Control IC)
Electrical characteristics for control part (Ta=25
℃
, Vin=18V,unless otherwise specified)
MIN
14.4
9
-
-
45
TYP
16
10
-
-
-
MAX
17.6
11
20
100
55
V
in(ON)
V
in(OFF)
I
in(ON)
I
in(OFF)
T
OFF(MAX)
Maximum OFF time
Minimum time for input of quasi
resonant signals *6
T
OFF(MIN)
Minimum OFF time *7
Vth(1)
O.C.P/F.B Pin threshold voltage 1
Vth(2)
O.C.P/F.B Pin threshold voltage 2
I
OCP/FB
O.C.P/F.B Pin extraction current
V
in(OVP)
O.V.P operation voltage
I
in(H)
V
in(La.OFF)
Latch circuit release voltage *8
Tj
(TSD)
Thermal shutdown operating temperature
V
in(SENSE)
Detected Voltage
-
Temperature coefficient of detected voltage
Operation start voltage
Operation stop voltage
Circuit current in operation
Circuit current in non-operation
V
V
Vin=0
→
17.6V
Vin=17.6
→
9V
-
Vin=14V
-
mA
μA
μsec
Tth(2)
-
-
-
-
1
2
μsec
μsec
V
V
mA
V
μA
-
-
-
0.68
1.3
1.2
34
-
0.73
1.45
1.35
36.5
-
0.78
1.6
1.5
39
400
-
Vin=0
→
39.0
V
6.6
140
31.7
-
-
-
8.4
-
32.3
-
V
℃
V
Vin=39.0
→
6.6V
-
Vin=31.7
→
32.3V
32
2.5
mV/
℃
Vin=31.7
→
32.3V
Latch circuit sustaining current *8
Definition
Symbol
Vin=39.0
→
8.5V
Ratings
Units
Test
Conditions
Electrical Characteristics (for MOSFET)
(Ta=25
℃
) unless otherwise specified
MIN
TYP
MAX
ID=300μA
V3
-2
=0V(short)
V
DS
=650V
V3-2=0V(short)
V3-2=10V
I
D
=1.2A
-
t
f
Switching time
-
-
250
nsec
Between channel and
internal frame
300
-
2
℃
/W
-
θ
ch-F
-
-
Thermal resistance
Symbol
μA
On-resistance
R
DS(ON)
-
-
1.9
Ω
Drain leakage current
I
DSS
V
DSS
650
-
-
Ratings
Units
Test Conditions
Drain-to-Source breakdown voltage
V
Definition
IRIS-G5653A
*6 Recommended operating conditions
Time for iunput of quasi resonant signals
For the quasi resonant signal inputted to OCP/FB Pin
at the time of quasi resonant operation, the signal shall
be wider thant Tth(2).
*7 The minimum OFF time means T
OFF
width at the time when the minimum quasi resonant signal is inputted.
*8 The latch circuit means a circuit operated O.V.P and T.S.D.
Vth(2)
Ｖ
O.C.P/F.B
Tth(2)
≧
1.0
μ
sec
0V
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