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參數(shù)資料
| 型號(hào)： | IRIS-F6456S |
| 廠商： | International Rectifier |
| 英文描述： | INTEGRATED SWITCHER |
| 中文描述： | 多功能開(kāi)關(guān) |
| 文件頁(yè)數(shù)： | 2/7頁(yè) |
| 文件大?。?/td> | 274K |
| 代理商： | IRIS-F6456S |
www.irf.com
*1 Refer to MOS FET A.S.O curve
*2 MOS FET Tch-EAS curve
*3 Refer to MOS FET Ta-PD1 curve
*4 Refer to TF-PD2 curve for Control IC (See page 5)
*5 Maximum switching current.
The maximum switching current is the Drain current determined by the drive voltage of the IC and
threshold voltage (Vth) of MOS FET. Therefore, in the event that voltage drop occurs between Pin 2 and
Pin 5 due to patterning, the maximum switching current decreases as shown by V
2-5
in Fig.1
Accordingly please use this device within the decrease value, referring to the derating curve of the
maximum switching current.
Absolute Maximum Ratings (Ta=25oC)
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are
absolute voltages referenced to terminals stated, all currents are defined positive into any lead. The thermal resistance and power
dissipation ratings are measured under board mounted and still air conditions.
Symbol
I
Dpeak
Definition
Terminals Max. Ratings
3-2
Units
A
Note
Drain Current *1
16
Single Pulse
V
2-5
=0.78V
Ta=-20~+125
℃
Single Pulse
I
L peak
=6.4A
Vin
Vth
Input voltage for control part
O.C.P/F.B Pin voltage
4-5
1-5
35
6
58
2.8
V
V
W
W
With infintite heatsink
Without heatsink
Specified by
Vin
×
Iin
Power dissipation for control part
(Control IC) *4
Internal frame temperature
in operation
Operating ambient temperature
Storage temperature
Channel temperature
Refer to recommended
operating temperature
Top
Tstg
Tch
-
-
-
-20 ~ +125
-40 ~ +125
150
℃
℃
℃
P
D1
Power dissipation for MOSFET *3
3-2
A
Single pulse avalanche energy *2
3-2
E
AS
521
mJ
Maximum switching current *5
3-2
I
DMAX
16
-
T
F
-20 ~ +125
℃
4-5
P
D2
0.49
W
V
2-5
Fig.1
IRIS-F6456S
Recommended operating conditions
Time for input of quasi resonant signals
For the quasi resonant signal inputted to O.C.P/F.B Pin
at the time of quasi resonant operation, the signal shall
be wider than T
th(2).
Vth(2)
Ｖ
O.C.P/F.B
Tth(2)
≧
1.0
μ
sec
0V
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