參數(shù)資料
型號(hào)： IR3092MTR
廠商： International Rectifier
英文描述： 2 PHASE OPTERON, ATHLON, OR VR10.X CONTROL IC
中文描述： 2相皓龍，速龍，或控制IC的VR10.X
文件頁(yè)數(shù)： 32/37頁(yè)
文件大?。?/td> 619K
代理商： IR3092MTR
IR3092
Page 32 of 37
06/25/04
LAYOUT GUIDELINES
The following layout guidelines are recommended to reduce the parasitic inductance and resistance of
the PCB layout, therefore minimizing the noise coupled to the IC. Refer to the schematic in Figure 6
–
System Diagram.
x
Dedicate at least one inner layer of the PCB as power ground plane (PGND).
x
The center pad of IC must be connected to ground plane (PGND) using the recommended via
pattern shown in “
PCB and Stencil Design Methodology
”.
x
The IC’s PGND1, 2 and LGND should connect to the center pad under IC.
x
The following components must be grounded directly to the LGND pin on the IC using a ground
plane on the component side of PCB: CSS, RSC2, RSET, and CVCC. The LGND should only be
connected to ground plane on the center pad under IC
x
Place the decoupling capacitors CVCC and CBIAS as close as possible to the VCC and VCCL
pins. The ground side of CBIAS should not be connected to LGND and it should directly be
grounded through vias.
x
The following components should be placed as close as possible to the respective pins on the
IC: RROSC, ROCSET, CDAC, RDAC, CSS, CSC2, RSC2, CCOMP RCOMP and RSET.
x
Place current sense capacitors CCS1, 2 and resistors RCS1, 2 as close as possible to CSINP1,
2 pins of IC and route the two current sense signals in pairs connecting to the IC. The current
sense signals should be located away from gate drive signals and switch nodes.
x
Use Kelvin connections to route the current sense traces to each individual phase inductor, in
order to achieve good current share between phases.
x
Place the input decoupling capacitors closer to the drain of top MOSFET and the source of the
bottom MOSFET. If possible, use multiple smaller value ceramic caps instead of one big cap, or
use low inductance type of ceramic cap, to reduce the parasitic inductance.
x
Route the high current paths using wide and short traces or polygons. Use multiple vias for
connections between layers.
x
The symmetry of the following connections from phase to phase is important for proper
operation:
-
The Kelvin connections of the current sense signals to inductors.
-
The gate drive signals from the IC to the MOSFETS.
-
The polygon shape of switching nodes.
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