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參數(shù)資料
| 型號： | IR3081MTR |
| 廠商： | International Rectifier |
| 英文描述： | XPHASE VR 10.0 CONTROL IC |
| 中文描述： | XPHASE村10.0控制IC |
| 文件頁數(shù)： | 14/20頁 |
| 文件大?。?/td> | 396K |
| 代理商： | IR3081MTR |
IR3081
Page 14 of 20
9/1/03
Processor Pins (0 = low, 1 = high)
VID4
VID3
VID2
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
1
1
0
Note: 3. Output disabled (Fault mode)
Processor Pins (0 = low, 1 = high)
VID4
VID3
VID2
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
0
0
1
0
0
1
0
VID1
VID0
VID5
Vout
(V)
0.8375
0.8500
0.8625
0.8750
0.8875
0.9000
0.9125
0.9250
0.9375
0.9500
0.9625
0.9750
0.9875
1.0000
1.0125
1.0250
1.0375
1.0500
1.0625
1.0750
1.0875
OFF
OFF
4
1.1000
1.1125
1.1250
1.1375
1.1500
1.1625
1.1750
1.1875
1.2000
VID1
VID0
VID5
Vout
(V)
1.2125
1.2250
1.2375
1.2500
1.2625
1.2750
1.2875
1.3000
1.3125
1.3250
1.3375
1.3500
1.3625
1.3750
1.3875
1.4000
1.4125
1.4250
1.4375
1.4500
1.4625
1.4750
1.4875
1.5000
1.5125
1.5250
1.5375
1.5500
1.5625
1.5750
1.5875
1.6000
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Table 1 - Voltage Identification (VID)
Adaptive Voltage Positioning
Adaptive voltage positioning is needed to reduce the output voltage deviations during load transients and the power
dissipation of the load when it is drawing maximum current. The circuitry related to voltage positioning is shown in
Figure 8. Resistor R
FB
is connected between the Error Amp’s inverting input pin FB and the converter’s output
voltage. An internal current source whose value is programmed by the same external resistor that programs the
oscillator frequency pumps current into the FB pin. The error amp forces the converter’s output voltage lower to
maintain a balance at its inputs. R
FB
is selected to program the desired amount of fixed offset voltage below the
DAC voltage.
The voltage at the VDRP pin is a buffered version of the share bus and represents the sum of the DAC voltage and
the average inductor current of all the phases. The VDRP pin is connected to the FB pin through the resistor RDRP.
Since the Error Amp will force the loop to maintain FB to be equal to the VDAC reference voltage, a current will be
flow into the FB pin equal to (VDRP-VDAC) / R
DRP
. When the load current increases, the adaptive positioning
voltage increases accordingly. More current flows through the feedback resistor R
FB
, and makes the output voltage
lower proportional to the load current. The positioning voltage can be programmed by the resistor R
DRP
so that the
droop impedance produces the desired converter output impedance. The offset and slope of the converter output
impedance are referenced to and therefore independent of the VDAC voltage.
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