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參數(shù)資料
| 型號： | IR3081M |
| 廠商： | International Rectifier |
| 英文描述： | XPHASE VR 10.0 CONTROL IC |
| 中文描述： | XPHASE村10.0控制IC |
| 文件頁數(shù)： | 17/20頁 |
| 文件大?。?/td> | 396K |
| 代理商： | IR3081M |
IR3081
Page 17 of 20
9/1/03
VCC
(12V)
START-UP
(ENABLE GATES
FAULT MODE)
NORMAL OPERATION
(VOUT CHANGES DUE TO LOAD
AND VID CHANGES)
HICCUP OVER-CURRENT
PROTECTION
RE-START
AFTER
OCP
POWER-DOWN
(VCC GATES
FAULT MODE)
8.9V
UVLO
SS/DEL
3.91V
1.3V
PWRGD
VOUT
IOUT
ENABLE
OCP
DELAY
OCP THRESHOLD
Figure 11 – Operating Waveforms
Power Good Output
The PWRGD pin is an open-collector output and should be pulled up to a voltage source through a resistor. During
soft start, the PWRGD remains low until the output voltage is in regulation and SS/DEL is above 3.91V. The
PWRGD pin becomes low if the fault latch is set. A high level at the PWRGD pin indicates that the converter is in
operation and has no fault, but does not ensure the output voltage is within the specification. Output voltage
regulation within the design limits can logically be assured however, assuming no component failure in the system.
Load Current Indicator Output
The IIN pin voltage represents the average current of the converter plus the DAC voltage. The load current can be
retrieved by subtracting the VDAC voltage from the IIN voltage.
System Reference Voltage (VBIAS)
The IR3081 supplies a 6.8V/5mA precision reference voltage from the VBIAS pin. The oscillator ramp trip points are
based on the VBIAS voltage so it should be used to program the Phase ICs phase delay to minimize phase errors.
Enable Input
Pulling the ENABLE pin below 0.6V sets the Fault Latch.
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