參數(shù)資料
型號(hào)： IR2113L6
英文描述： SINGLE MOSFET DRIVER|CMOS|DIP|14PIN|CERAMIC
中文描述： 單MOSFET驅(qū)動(dòng)器|的CMOS |雙酯| 14PIN |陶瓷
文件頁數(shù)： 2/15頁
文件大?。?/td> 275K
代理商： IR2113L6
2
IR2110/IR2113
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions. Additional information is shown in Figures 28 through 35.
www.irf.com
Symbol
V
B
Definition
Min.
-0.3
Max.
525
Units
High side floating supply voltage (IR2110)
(IR2113)
-0.3
625
V
S
V
HO
V
CC
V
LO
V
DD
V
SS
V
IN
dV
s
/dt
P
D
High side floating supply offset voltage
V
B
- 25
V
S
- 0.3
-0.3
V
B
+ 0.3
V
B
+ 0.3
25
High side floating output voltage
Low side fixed supply voltage
Low side output voltage
-0.3
V
CC
+ 0.3
V
SS
+ 25
V
CC
+ 0.3
V
DD
+ 0.3
50
Logic supply voltage
-0.3
Logic supply offset voltage
V
CC
- 25
V
SS
- 0.3
—
Logic input voltage (HIN, LIN & SD)
Allowable offset supply voltage transient (figure 2)
Package power dissipation @ T
A
≤
+25°C
V/ns
(14 lead DIP)
—
1.6
(14 lead DIP w/o lead 4)
—
1.5
(16 lead DIP w/o leads 4 & 5)
—
1.6
(16 lead SOIC)
—
1.25
R
THJA
Thermal resistance, junction to ambient
(14 lead DIP)
—
75
(14 lead DIP w/o lead 4)
—
85
(16 lead DIP w/o leads 4 & 5)
—
75
(16lLead SOIC)
—
100
T
J
T
S
T
L
Junction temperature
—
150
Storage temperature
-55
150
°C
Lead temperature (soldering, 10 seconds)
—
300
Symbol
V
B
V
S
Definition
Min.
V
S
+ 10
Note 1
Max.
V
S
+ 20
500
Units
High side floating supply absolute voltage
High side floating supply offset voltage (IR2110)
(IR2113)
Note 1
600
V
HO
V
CC
V
LO
V
DD
V
SS
V
IN
T
A
High side floating output voltage
V
S
10
V
B
20
Low side fixed supply voltage
Low side output voltage
0
V
CC
Logic supply voltage
V
SS
+ 4.5
-5
V
SS
+ 20
5
Logic supply offset voltage
Logic input voltage (HIN, LIN & SD)
V
SS
-40
V
DD
125
Ambient temperature
°C
Recommended Operating Conditions
The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the
recommended conditions. The VS and VSS offset ratings are tested with all supplies biased at 15V differential. Typical
ratings at other bias conditions are shown in figures 36 and 37.
Note 1: Logic operational for V
S
of -4 to +500V. Logic state held for V
S
of -4V to -V
BS
.
°C/W
W
V
V
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