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參數(shù)資料
| 型號(hào)： | IQ80C154-30 |
| 英文描述： | CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller |
| 中文描述： | 的CMOS 0至36 MHz的單芯片8位微控制器 |
| 文件頁(yè)數(shù)： | 18/24頁(yè) |
| 文件大小： | 354K |
| 代理商： | IQ80C154-30 |
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Rev.F (14 Jan. 97)
18
MATRA MHS
XTAL1
TCHCL = 5 ns, VIL = VSS + .5 V, VIH = VCC –.5 V ;
slighty higher if a crystal oscillator used.
Idle ICC is measured with all otput pins disconnected ;
disconnect ICC is measurdriven
VSS + 5 V, VIH = VCC -.5 V ; XTAL2 N.C ; Port
0 = VCC ; EA = RST = VSS.
Power Down ICC is measured with all output pins
disconnected ; EA = PORT 0 = VCC ; XTAL2 N.C. ;
RST = VSS.
Note 2 :
Capacitance loading on Ports 0 and 2 may cause
spurious noise pulses to be superimposed on the VOLS of
ALE and Ports 1 and 3. The noise is due to external bus
capacitance discharging into the Port 0 and Port 2 pins
when these pins make 1 to 0 transitions during bus
operations. In the worst cases (capacitive loading 100
pF), the noise pulse on the ALE line may exceed 0.45 V
may exceed 0,45 V with maxi VOL peak 0.6 V A Schmitt
Trigger use is not necessary.
with
TCLCH,
Figure 16. ICC Test Condition, Active Mode.
All other pins are disconnected.
Figure 17. ICC Test Condition, Power Down Mode.
All other pins are disconnected.
Figure 18. Clock Signal Waveform for ICC Tests in Active and Idle Modes. TCLCH = TCHCL = 5 ns.
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