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參數(shù)資料
| 型號： | IP-ED8B10B |
| 元件分類： | 通信、網(wǎng)絡(luò)模塊及開發(fā)工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數(shù)據(jù)通信 |
| 文件頁數(shù)： | 6/11頁 |
| 文件大?。?/td> | 502K |
| 代理商： | IP-ED8B10B |
6
Altera Corporation
8b10b Encoder/Decoder MegaCore Function (ED8B10B) Data Sheet
Encoding Latency
The encoder is pipelined, thus it takes three clock cycles for a character to
be encoded. The encoded value—corresponding to the values of
datain
and
kin
sampled by the encoder on rising edge
n
—is output shortly after
rising edge
n+2
, and is available to be sampled on the rising edge of clock
cycle
n+3
. (See
Figure 4 on page 7
).
To enable cascaded encoding, the data paths fed by the
rdforce
and
rdin
inputs are not pipelined. Since
rdforce
and
rdin
are normally
only used in cascaded configurations, this should not be a problem.
In cases where the
rdforce
and
rdin
inputs are to be used in non-
cascaded configurations, they should be delayed two clock cycles with
respect to their corresponding
datain
and
kin
values. This can be
achieved by inserting two registers in series with each of the inputs to be
delayed, the following example Verilog code shows how to implement the
required delay registers.
Example:
Adding delay to
rdforce
and
rdin
for non-cascaded
applications:
// The _pre2 registers are set at the same time as datain and kin.
reg
rdforce_pre2;
reg
rdin_pre2;
// The _pre1 registers provide an extra clock tick of delay
reg
rdforce_pre1;
reg
rdin_pre1;
always
@ (posedge clk)
begin
rdforce <= rdforce_pre1;
rdforce_pre1 <= rdforce_pre2;
rdin <= rdin_pre1;
rdin_pre1 <= rdin_pre2;
end
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