參數(shù)資料
型號(hào)： INTELDX4
廠商： Intel Corp.
英文描述： Embedded Write-Back Enhanced Processor(32位回復(fù)嵌入式增強(qiáng)型處理器)
中文描述： 嵌入式回寫增強(qiáng)型處理器（32位回復(fù)嵌入式增強(qiáng)型處理器）
文件頁(yè)數(shù)： 1/50頁(yè)
文件大小： 534K
代理商： INTELDX4
INTEL CORPORATION, 1997
December 1997
Order Number:
272771-002
EMBEDDED WRITE-BACK ENHANCED
IntelDX4 PROCESSOR
Figure 1.
Embedded Write-Back Enhanced IntelDX4
Processor Block Diagram
I
Up to 100 MHz Operation
I
Integrated Floating-Point Unit
I
Speed-Multiplying Technology
I
32-Bit RISC Technology Core
I
16-Kbyte Write-Back Cache
I
3.3 V Core Operation with 5 V Tolerant
I/O Buffers
I
Burst Bus Cycles
I
Dynamic Bus Sizing for 8- and 16-bit
Data Bus Devices
I
SL Technology
I
Data Bus Parity Generation and Checking
I
Boundary Scan (JTAG)
I
3.3-Volt Processor, 75 MHz, 25 MHz CLK
— 208-Lead Shrink Quad Flat Pack (SQFP)
I
3.3-Volt Processor, 100 MHz, 33 MHz CLK
— 208-Lead Shrink Quad Flat Pack (SQFP)
— 168-Pin Pin Grid Array (PGA)
I
Binary Compatible with Large Software
Base
Paging
Unit
Prefetcher
32-Byte Code
Queue
2 x 16 Bytes
Code
Stream
Floating
Point Unit
Barrel
Shifter
24
Cache Unit
Burst Bus
Control
Bus Control
Write Buffers
4 x 32
64-Bit Interunit Transfer Bus
Register
File
ALU
Segmentation
Unit
Descriptor
Registers
Limit and
Attribute PLA
32
Base/
Index
Bus
Translation
Lookaside
Buffer
20
16 Kbyte
Cache
Clock
Multiplier
Floating
Point
Register File
Control &
Protection
Test Unit
Control
ROM
Address
Drivers
CLK
Core
Clock
32
Data Bus
Transceivers
32
Request
Sequencer
Bus Size
Control
Cache
Control
Parity
Generation
and Control
Boundary
Scan
Control
Bus Interface
D31-D0
A31-A2 BE3#- BE0#
ADS# W/R# D/C# M/IO# PCD
PWT RDY# LOCK# PLOCK#
BOFF# A20M# BREQ HOLD
HLDA RESET SRESET INTR
NMI SMI# SMIACT# FERR#
IGNNE# STPCLK#
BRDY# BLAST#
BS16# BS8#
KEN# FLUSH# AHOLD EADS#
CACHE# HITM# INV WB/WT#
TCK TMS TDI TDO
1
Instruction
Decode
32
Decoded
Instruction
Path
PCD
PWT
2
Physical
Address
32-Bit Data Bus
32-Bit Data Bus
Linear Address
Micro-
Instruction
Displacement Bus
PCHK# DP3-DP0
32
A3232-01
32
CLKMUL
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