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參數(shù)資料
| 型號： | INTEL387DX |
| 英文描述： | Intel387 DX - MATH COPROCESSOR |
| 中文描述： | Intel387霉素-數(shù)學(xué)協(xié)處理器 |
| 文件頁數(shù)： | 28/41頁 |
| 文件大?。?/td> | 435K |
| 代理商： | INTEL387DX |
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Intel387
TM
DX MATH COPROCESSOR
3.4.3 BUS CYCLES OF MIXED TYPE
When the Intel387 DX MCP bus logic is in the T
RS
state, it distinguishes between nonpipelined and
pipelined cycles according to the behavior of ADS
Y
and
READY
Y
.
In
a
nonpipelined
READY
Y
is activated, and the transition is from T
RS
to idle state. In a pipelined cycle, both READY
Y
and
ADS
Y
are active and the transition is first from T
RS
state to T
P
state then, after one clock period, back
to T
RS
state.
cycle,
only
3.4.4 BUSY
Y
AND PEREQ TIMING
RELATIONSHIP
Figure 3.8 shows the activation of BUSY
Y
at the
beginning of instruction execution and its deactiva-
tion after execution of the instruction is complete.
When possible, the Intel387 DX MCP may deacti-
vate BUSY
Y
prior to the completion of the current
instruction allowing the CPU to transfer the next in-
struction’s opcode and operands. PEREQ is activat-
ed in this interval. If ERROR
Y
(not shown in the
diagram) is ever asserted, it would occur at least six
CPUCLK2 periods after the deactivation of PEREQ
and at least six CPUCLK2 periods before the deacti-
vation of BUSY
Y
. Figure 3.8 shows also that STEN
is activated at the beginning of a bus cycle.
240448–11
Cycle 1–Cycle 4 represent the operand transfer cycle for an instruction involving a transfer of two 32-bit loads in total.
The opcode write cycles and other overhead are not shown.
Note that the next cycle will be a pipelined cycle if both READY
Y
and ADS
Y
are sampled active at the end of a T
RS
state of the current cycle.
Figure 3.6. Fastest Transitions to and from Pipelined Cycles
28
28
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