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參數(shù)資料
| 型號： | INTEGRA |
| 英文描述： | Integra L64754 ISDB-S DVB/DSS Satellite Receiver |
| 中文描述： | INTEGRA的L64754的ISDB - ?的DVB / DSS的衛(wèi)星接收機 |
| 文件頁數(shù)： | 2/2頁 |
| 文件大?。?/td> | 29K |
| 代理商： | INTEGRA |
For more information please call:
LSI Logic Corporation
North American Headquarters
Milpitas, CA
Tel: 866 574 5741
LSI Logic Europe Ltd.
European Headquarters
United Kingdom
Tel: 44 1344 426544
Fax: 44 1344 481039
LSI Logic KK Headquarters
Tokyo, Japan
Tel: 81 3 5463 7165
Fax 81 3 5463 7820
LSI: Logic w eb site:
www.lsilogic.com
LSI Logic logo design, The Communications
Company and Integra are either registered trade-
marks or trademarks of LSI Logic Corporation. All
other brand and product names may be trade-
marks of their respective companies.
LSI Logic Corporation reserves the right to make
changes to any products and services herein at
any time without notice. LSI Logic does not assume
any responsibility or liability arising out of the
application or use of any product or service
described herein, except as expressly agreed to in
writing by LSI Logic; nor does the purchase, lease,
or use of a product or service from LSI Logic con-
vey a license under any patent rights, copyrights,
trademark rights, or any other of the intellectual
property rights of LSI Logic or of third parties.
Copyright 2001 by LSI Logic Corporation.
All rights reserved.
Order No. I20096
1201.1k.JG.IK - Printed in USA
The
Communica tions
Compa ny
TM
Integra
L64754 ISDB-S, DVB/ DSS Satellite Receiver
The Forward Error Correction (FEC) decoder pipeline is a complete FEC
concatenated decoder utilizing a TCM inner code in ISDB-S mode and Viterbi
inner code in DVB/ DSS mode with Reed-Solomon outer code. The FEC
decoding pipeline contains necessary synchronizations-de-interleaving and
scrambling functions-for a complete decoding solution.
ISDB- S MODE:
B/ Q/ 8PSK demodulation for 28.86 Mbaud
TMCC based synchronization
Frame synchronization with input frequency error of less than +/ - 720KHz
for fast carrier acquisition
Programmable frame and super frame synchronization, enabling fast and
reliable frame acquisition
On-chip digital carrier synchronization featuring AFC for coarse
acquisition and frequency sweep for fine acquisition
Pragmatic TCM decoder module for rates 1/ 2, 2/ 3, 3/ 4, 5/ 6, and 7/ 8
(204/ 188), (64/ 48) Reed-Solomon decoder
Mask control option for choice of transmission layers (i.e., supports
“
graceful degradation
”
, under severe environmental conditions)
On-chip transport stream divider allowing user selection of one-of-eight
(or all) interleaved TS streams
Output PCR jitter less than IOOns
DV B/ DSS MODE SUPPORTS:
DVB and DSS system specifications
Synchronous Parallel Interface protocol for FEC data output
REFERENCE DESIGN BOARD
To accelerate development of set-top box solutions, the L64754 is available
with a developer
’
s kit that allows manufacturers to select the best option for
their target market and application requirements. The kit provides the hard-
ware and software components to shorten development cycles and to ensure
fast time-to-market.
The reference design board consists of a complete evaluation board with
a PC interface and MPEG-2 transport output. Software to enable system
resting and code optimization is included, along with a manual that provides
test and evaluation information and PC board layout. Complete micro code
for the L64754
’
s micro controller is included, with the option of customizing
the micro code.
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