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參數(shù)資料
IN74LV573
1
O
CTAL
D-T
YPE
T
RANSPARENT
L
ATCH
(3-S
TATE
)
By pinning IN74LV573 are compatible with IN74HC573A and
IN74HCT573A series. Input voltage levels are compatible with
stadard CMOS levels.
Output voltage levels are compatible with input levels of CMOS,
NMOS and TTL IC
S
Voltage supply range from 1.2 to 5.5 V
LOW input current: 1.0
μ
А
; 0.1
μ
А
at
Т
= 25
°
С
Output current 8 m
А
Latch current: not less than150 m
А
at
Т
= 125
°
С
ESD acceptable value: not less than 2000 V as per HBM and
not less than 200 V as per MM
FUNCTION TABLE
Inputs
OE
LE
D
L
H
H
L
H
L
L
L
X
Outputs
Q
H
L
no
change
Z
H
H -HIGH voltage level
L - LOW voltage level
X - don’t care
Z - High impedance state
X
X
ORDERING INFORMATION
IN74LV573N Plastic DIP
IN74LV573D SOIC
T
A
= -40
°
to 125
°
C
for all packages
PIN ASSIGNMENT
1
2
3
5
4
6
7
8
9
10
V
CC
20
18
17
16
15
14
19
11
12
13
GND
OE
D0
D1
D2
Q1
Q0
Q2
D3
D4
D5
D6
Q3
Q4
Q5
Q6
Q7
LE
D7
相關PDF資料 |
PDF描述 |
|---|---|
| IN74LV573D | Replaced by SN74ABT7819A : 512 x 18 x 2 bidirectional synchronous FIFO memory 80-QFP 0 to 70 |
| IN74LV573N | Replaced by SN74ABT7819A : 512 x 18 x 2 bidirectional synchronous FIFO memory 80-LQFP 0 to 70 |
| IN74LV574DW | Octal D-type flip-flop; positive edge-trigger (3-State) |
| IN74LV574N | Octal D-type flip-flop; positive edge-trigger (3-State) |
| IN74LV574 | Replaced by SN74ABT7819A : 512 x 18 x 2 bidirectional synchronous FIFO memory 80-QFP 0 to 70 |
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