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參數(shù)資料
| 型號： | IN74ACT112N |
| 廠商： | INTEGRAL JOINT STOCK COMPANY |
| 英文描述： | DUAL J-K FLIP-FLOP WITH SET AND RESET |
| 中文描述： | 雙JK觸發(fā)器與SET和RESET |
| 文件頁數(shù)： | 1/5頁 |
| 文件大小： | 202K |
| 代理商： | IN74ACT112N |
IN74ACT112
1
D
UAL
J-K
F
LIP
-F
LOP
WITH
S
ET AND
R
ESET
High-Speed Silicon-Gate CMOS
The IN74ACT112 is identical in pinout to the LS/ALS112,
HC/HCT112. The IN74ACT112 may be used as a level converter
for interfacing TTL or NMOS outputs to High Speed CMOS
inputs.
Each flip-flop is negative-edge clocked and has active-low
asynchronous Set and Reset inputs.
TTL/NMOS Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0
μ
A; 0.1
μ
A @ 25
°
C
Outputs Source/Sink 24 mA
ORDERING INFORMATION
IN74ACT112N Plastic
IN74ACT112D SOIC
T
A
= -40
°
to 85
°
C for all
packages
FUNCTION TABLE
Inputs
Clock
X
X
X
L
H
Outputs
Q
H
L
L
*
No Change
L
H
Toggle
No Change
No Change
No Change
Set
L
H
L
H
H
H
H
H
H
H
Reset
H
L
L
H
H
H
H
H
H
H
J
X
X
X
L
L
H
H
X
X
X
K
X
X
X
L
H
L
H
X
X
X
Q
L
H
L
*
H
L
* Both outputs will remain low as long as Set and
Reset are low, but the output states are
unpredictable if Set and Reset go high
simultaneously
X = Don’t Care
LOGIC DIAGRAM
PIN 16=V
CC
PIN 8 = GND
PIN ASSIGNMENT
相關PDF資料 |
PDF描述 |
|---|---|
| IN74ACT11 | TRIPLE 3-INPUT AND GATE |
| IN74ACT11D | TRIPLE 3-INPUT AND GATE |
| IN74ACT11N | TRIPLE 3-INPUT AND GATE |
| IN74ACT125 | Quad 3-State Noninverting Buffers |
| IN74ACT125D | Quad 3-State Noninverting Buffers |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IN74ACT11D | 制造商:INTEGRAL 制造商全稱:INTEGRAL 功能描述:TRIPLE 3-INPUT AND GATE |
| IN74ACT11N | 制造商:INTEGRAL 制造商全稱:INTEGRAL 功能描述:TRIPLE 3-INPUT AND GATE |
| IN74ACT125 | 制造商:INTEGRAL 制造商全稱:INTEGRAL 功能描述:Quad 3-State Noninverting Buffers |
| IN74ACT125D | 制造商:INTEGRAL 制造商全稱:INTEGRAL 功能描述:Quad 3-State Noninverting Buffers |
| IN74ACT125N | 制造商:INTEGRAL 制造商全稱:INTEGRAL 功能描述:Quad 3-State Noninverting Buffers |
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