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參數(shù)資料
| 型號： | IMSSG559AYB |
| 英文描述： | CPU System Clock Generator |
| 中文描述： | CPU系統(tǒng)時鐘發(fā)生器 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 87K |
| 代理商： | IMSSG559AYB |
SG559
Mobile Pentium
Processor Application Clock Generator with SSCG, USB and Power
Management Support
Approved Product
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571
Rev. 1.0
4/12/1999
Page 3 of 8
POWER MANAGEMENT FUNCTIONS
All PCI (excluding PCI_F) and CPU clocks can be enabled or stopped via the PCI_STOP# and CPU_STOP# input pins.
All clocks are stopped in the low state. All clocks maintain a valid high period on transitions from running to stopped and
on transitions from stopped to running when the chip was not powered down. On power up, the VCOs will stabilize to
the correct pulse widths within 0.2 mS. The CPU and PCI clocks transition between running and stopped by waiting for
one positive edge on PCI_F followed by a negative edge on the clock of interest, after which high levels of the output are
either enabled or disabled.
PWR_DWN#
1
1
1
1
0
CPU_STOP#
0
0
1
1
x (don’t care)
PCI_STOP#
0
1
0
1
x (don’tcare)
CPUCLK
LOW
LOW
RUNNING
RUNNING
LOW
PCICLK
LOW
RUNNING
LOW
RUNNING
LOW
OTHER CLKs
RUNNING
RUNNING
RUNNING
RUNNING
LOW
XTAL & VCOs
RUNNING
RUNNING
RUNNING
RUNNING
OFF
POWER MANAGEMENT TIMING
PCI_F
PCI_STOP#
PCICLK(1:5)
CPU_STOP#
CPUCLK(0:1)
POWER MANAGEMENT TIMING
Latency
Signal
Signal State
No. of rising edges of free
running PCICLK (PCIF)
1
1
1
1
CPU_ST0P#
0 (disabled)
1 (enabled)
0 (disabled)
1 (enabled)
PCI_ST0P#
NOTES:
1. Clock on/off latency is defined in the number of rising edges of free running PCI CLOCK between the clock disable
goes low/high to the first valid clock comes out of the device.
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