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參數(shù)資料
| 型號(hào)： | IMSA110 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Image and Signal Processing SUB-System(圖像和信號(hào)處理子系統(tǒng)) |
| 中文描述： | 圖像和信號(hào)處理子系統(tǒng)（圖像和信號(hào)處理子系統(tǒng)） |
| 文件頁數(shù)： | 1/13頁 |
| 文件大?。?/td> | 177K |
| 代理商： | IMSA110 |
AN547/07/92
CASCADING IMSA110s
APPLICATION NOTE
1.
INTRODUCTION
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
2.
2.1
2.2
OPERATION OF A SINGLE IMSA110
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
One dimensional operation of an IMS A110. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Two dimensional operation of an IMS A110. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
1
2
3.
FUNDAMENTALS OF CASCADING IMSA110s
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
4.
CASCADING IMSA110s TO PRODUCE LONG ONE DIMENSIONAL FILTERS
. . . . . . .
4
5.
CASCADING IMSA110s TO PRODUCE WIDER TWO DIMENSIONAL FILTERS
. . . . . .
5
6.
CASCADING IMSA110s TO PRODUCE HIGHER TWO DIMENSIONAL FILTERS
. . . . .
5
7.
CASCADING IMSA110s TO PRODUCE WIDER AND HIGHER
. . . . . . . . . . . . . . . . . . . .
TWO DIMENSIONAL FILTERS
7
8.
CASCADING IMSA110s TO PERFORM MULTI PASS FILTERING OPERATIONS
. . . . .
8
9.
9.1
9.2
9.3
CASCADING IMSA110s FOR INCREASED DATA PRECISION
. . . . . . . . . . . . . . . . . . . .
Increasing data precision with an external 22 bit adder . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Increasing data precision with an external delay line. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Increasing data precision with no external hardware. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
9
10
11
10.
10.1 Increasing coefficient precision with an external 22 bit adder . . . . . . . . . . . . . . . . . . . . . . .
10.2 Increasing coefficient precision with an external delay line . . . . . . . . . . . . . . . . . . . . . . . . .
10.3 Increasing coefficient precision with no external hardware . . . . . . . . . . . . . . . . . . . . . . . . .
CASCADING IMS A110s FOR INCREASED COEFFICIENT PRECISION
. . . . . . . . . . . .
11
11
12
13
11.
SUMMARY
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13
1. INTRODUCTION
The IMSA110 is a single-chip programmable and
cascadable device suitable for many high speed
image and signal processing applications. It con-
sists of a configurable array of multiply-accumula-
tors (420 MOPs), three programmable length 1120
tage shift registers, a versatile post-processing unit
and a microprocessor interface for configuration
and control purposes. The comprehensive on-chip
facilities makes a single device capable of dealing
with many image processing operations. A simpli-
fied block diagram is shown in Figure 1.
For some applications however, the power and
versatility of a single IMSA110 is not sufficient, in
these cases a cascade of devices often provides a
solution. The purpose of this document is to de-
scribe some of the most useful ways to cascade
IMSA110s to achieve even higher performance and
as such does not cover the use of the backend
processor or device applications.
2. OPERATION OF A SINGLE IMSA110
The A110 may be set up as either a one or two
dimensional multiplier accumulator array (MAC).
2.1 One dimensional operation of an IMSA110
For one dimensional operation the first delay PSRc
is set to some arbitrary value (normally zero) while
PSRb and PSRa are set to zero. N.B. at any given
point in time the first MAC stage in bank c is
1/13
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