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參數(shù)資料
| 型號(hào)： | IMP813LCPA |
| 廠商： | IMP INC. |
| 英文描述： | LOW-POWER レP SUPERVISOR CIRCUITS |
| 中文描述： | 低功耗レP監(jiān)控電路 |
| 文件頁(yè)數(shù)： | 5/9頁(yè) |
| 文件大小： | 167K |
| 代理商： | IMP813LCPA |
1999 IMP, Inc.
408-432-9100/www.impweb.com
5
IMP705/6/7/8, 8
1
1
3L
Detail Descriptions
RESET/RESET Operation
The RESET/RESET signals are designed to start a
μ
P/
μ
C in a
known state or return the system to a known state.
The IMP707/708 have two RESET outputs, one active-HIGH
RESET and one active-LOW RESET output. The IMP813L has
only an active-HIGH output. RESET is simply the complement
of RESET.
RESET is guaranteed to be LOW with V
CC
above 1.2V. During a
power-up sequence, RESET remains low until the supply rises
above the threshold level, either 4.65V, 4.40V or 4.00V. RESET goes
high approximately 200ms after crossing the threshold.
During power-down, RESET goes LOW as V
CC
falls below the
threshold level and is guaranteed to be under 0.4V with V
CC
above 1.2V.
In a brownout situation where V
CC
falls below the threshold
level, RESET pulses low. If a brownout occurs during an already-
initiated reset, the pulse will continue for a minimum of 140ms.
Auxiliary Comparator
All devices have an auxiliary comparator with 1.25V trip point
and uncommitted output (PFO) and noninverting input (PFI).
This comparator can be used as a supply voltage monitor with an
external resistor voltage divider. The attenuated voltage at PFI
should be set just below the 1.25 threshold. As the supply level
falls, PFI is reduced causing the PFO output to transit LOW.
Normally PFO interrupts the processor so the system can be shut
down in a controlled manner.
5V
0V
5V
t
WD
t
RS
t
WP
t
WD
t
WD
0V
5V
0V
5V
0V
RESET triggered by MR
WDI
WDO
RESET
IMP813L
(RESET)
705_05.eps
Figure 1. WDI Three-state operation
Figure 2. Watchdog Timing
5V
0V
5V
0V
5V
0V
5V
0V
V
CC
v
RT
WDO
RESET
MR
t
MD
t
RS
t
RS
t
MR
MR extermally
set low
705_04.eps
Manual Reset (MR)
The active-LOW manual reset input is pulled high by a 250
μ
A
pull-up current and can be driven low by CMOS/TTL logic or a
mechanical switch to ground. An external debounce circuit is
unnecessary since the 140ms minimum reset time will debounce
mechanical pushbutton switches.
By connecting the watchdog output (WDO) and MR, a watchdog
timeout forces RESET to be generated. The IMP813L should be
used when an active-HIGH RESET is required.
Watchdog Timer
The watchdog timer available on the IMP705/706/813L monitors
μ
P/
μ
C activity. If activity is not detected within 1.6 seconds, the
internal timer puts the watchdog output, WDO, into a LOW
state. WDO will remain LOW until activity is detected at WDI.
The watchdog function is disabled, meaning it is cleared and not
counting, if WDI is floated or connected to a three-stated circuit.
The watchdog timer is also disabled if RESET is asserted. When
RESET becomes inactive and the WDI input sees a high or low
transition as short as 50ns, the watchdog timer will begin a 1.6
second countdown. Additional transitions at WDI will reset the
watchdog timer and initiate a new countdown sequence.
WDO will also become LOW and remain so, whenever the
supply voltage, V
CC
, falls below the device threshold level. WDO
goes HIGH as soon as V
CC
transitions above the threshold. There
is no minimum pulse width for WDO as there is for the RESET
outputs. If WDI is floated, WDO essentially acts as a low-power
output indicator.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| IMP813LCSA | 制造商:IMP 制造商全稱:IMP 功能描述:LOW-POWER レP SUPERVISOR CIRCUITS |
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| IMP813LESA | 制造商:IMP 制造商全稱:IMP 功能描述:LOW-POWER レP SUPERVISOR CIRCUITS |
| IMP8-1A0-00-A-XXX | 制造商:ASTEC 制造商全稱:Astec America, Inc 功能描述:Intelligent MP Series Up to 1500 Watts |
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