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參數(shù)資料
| 型號(hào)： | IMP5218 |
| 廠商： | IMP INC. |
| 英文描述： | 9--Liine Pllug and Pllay SCSII Termiinattor |
| 中文描述： | 9 - Liine Pllug和Pllay SCSII Termiinattor |
| 文件頁數(shù)： | 1/10頁 |
| 文件大?。?/td> | 217K |
| 代理商： | IMP5218 |
Key Features
N
SCSI plug and play
— Dual disconnect pins
— Logic LOW disconnects lines
N
Hot swap compatible
N
Ultra-Fast response for Fast-20 SCSI applications
N
35MHz channel bandwidth
N
3.5V operation
N
Less than 3pF output capacitance
N
375μA disable-mode current
N
Thermally self limiting
N
No external compensation capacitors
N
Implements 8-bit or 16-bit (wide) applications
N
Compatible with active negation drivers
(60mA/channel)
N
Compatible with passive and active terminations
N
Approved for use with SCSI 1, 2, 3 and UltraSCSI
Block Diagrams
DISCONNECT 1
DISCONNECT 2
Current
Biasing
Circuit
Thermal
Limiting
Circuit
24mA Current
Limiting Circuit
Term Power
DATA OUTPUT
PIN DB (0)
1 of 9 Channels
2.85V
5218_01.eps
9-Line Plug and Pla
y
y
SCSI T
er
er
minat
The 9-channel IMP5218 SCSI terminator is part of IMP's family of high-
performance SCSI terminators that deliver true UltraSCSI performance.
The BiCMOS design offers superior performance over first generation
linear regulator/ resistor based terminators.
or
The IMP5218 has two disconnect pins for SCSI Plug and Play (PnP)
applications.
IMP's new architecture employs high-speed adaptive elements for each
channel, thereby providing the fastest response possible - typically
35MHz, which is 100 times faster than the older linear regulator termi-
nator approach. The bandwidth of terminators based on the older
regulator/ resistor terminator architecture is limited to 500kHz since a
large output stabilization capacitor is required. The IMP architecture
eliminates the external output compensation capacitor and the need
for transient output capacitors while maintaining pin compatibility
with first generation designs. Reduced component count is inherent
with the IMP5218.
The IMP5218 architecture tolerates marginal system designs. A key
improvement offered by the IMP5218 lies in its ability to insure reliable,
error-free communications even in systems which do not adhere to rec-
ommended SCSI hardware design guidelines, such as improper cable
lengths and impedance. Frequently, this situation is not controlled by the
peripheral or host designer.
For portable and configurable peripherals, the IMP5218 can be placed in
a sleep mode with two disconnect signals. When disabled, the quiescent
current is typically 375
μ
A, and the outputs are in a high impedance state.
IMP5
IMP52
1
1
1
1/5
1
1
1
8
Data Communications
1
D
ATA
C
OMMUNICATIONS
Daily Silver IMP
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| IMP5219 | 制造商:IMP 制造商全稱:IMP 功能描述:9--Liine SCSII Termiinattor |
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