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參數(shù)資料
| 型號(hào)： | IMP5112CPWPT |
| 廠商： | IMP INC. |
| 英文描述： | 9--Liine SCSII Termiinattor - 35MHz Channell Bandwiidtth |
| 中文描述： | 9 - Liine SCSII Termiinattor -達(dá)到35MHz納爾Bandwiidtth |
| 文件頁(yè)數(shù)： | 1/6頁(yè) |
| 文件大?。?/td> | 149K |
| 代理商： | IMP5112CPWPT |
Key Features
N
Ultra-Fast response for Fast-20 SCSIapplications
N
35MHz channel bandwidth
N
3.3V operation
N
Less than 3pF output capacitance
N
Sleep-mode current less than 275μA
N
Thermally self limiting
N
No external compensation capacitors
N
Implements 8-bit or 16-bit (wide) applications
N
Compatible with active negation drivers
(60mA/channel)
N
Compatible with passive and active terminations
N
Approved for use with SCSI1, 2, 3 and UltraSCSI
N
Hot swap compatible
N
Pin-for-pin compatible with LX5211 and
UC5606 (IMP5111)
N
Pin-for-pin compatible with LX5212 and
UC5603/5613/5614 (IMP5112)
Block Diagrams
–
+
Current
Biasing
Circuit
Thermal
Limiting
Circuit
24mA Current
Limiting Circuit
Term Power
DATA OUTPUT
PIN DB (0)
1 of 9 Channels
DISCONNECT (IMP5111)
DISCONNECT (IMP5112)
1.4V
2.85V
5111/5112_01.eps
9-Line SCSI T
er
er
– 35MHz Channel Bandwidt
h
h
minat
or
The 9-channel IMP5111/ 5112 SCSI terminator is part of IMP's family
of high-performance SCSI terminators that deliver true UltraSCSI per-
formance. The BiCMOS design offers superior performance over first
generation linear regulator/ resistor based terminators.
IMP's new architecture employs high-speed adaptive elements for each
channel, thereby providing the fastest response possible - typically
35MHz, which is 100 times faster than the older linear regulator termi-
nator approach. The bandwidth of terminators based on the older
regulator/ resistor terminator architecture is limited to 500kHz since a
large output stabilization capacitor is required. The IMP architecture
eliminates the external output compensation capacitor and the need
for transient output capacitors while maintaining pin compatibility
with first generation designs. Reduced component count is inherent
with the IMP5111/ 5112.
The IMP5111/ 5112 architecture tolerates marginal system designs. A key
improvement offered by the IMP5111/ 5112 lies in its ability to insure
reliable, error-free communications even in systems which do not adhere
to recommended SCSI hardware design guidelines, such as improper
cable lengths and impedance. Frequently, this situation is not controlled
by the peripheral or host designer.
For portable and configurable peripherals, the IMP5111/ 5112 can be
placed in a sleep mode with a disconnect signal. Quiescent current is less
than 275
μ
A when disabled. When disabled, the outputs are in a high
impedance state with output capacitance less than 3pF.
1
IMP5
1
1
1/5
1
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ATA
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OMMUNICATIONS
Daily Silver IMP www.ds-imp.com.cn
相關(guān)PDF資料 |
PDF描述 |
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| IMP5111 | 9-Line SCSI Terminator -35MHz Channel Bandwidth(9線(xiàn)SCSI終端,35MHz通道帶寬) |
| IMP5115 | 9-Line SCSI Ter erminat minator |
| IMP5115CD | 9-Line SCSI Ter erminat minator |
| IMP5115CDT | 9-Line SCSI Ter erminat minator |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IMP5115 | 制造商:IMP 制造商全稱(chēng):IMP 功能描述:9-Line SCSI Ter erminat minator |
| IMP5115CD | 制造商:IMP 制造商全稱(chēng):IMP 功能描述:9-Line SCSI Ter erminat minator |
| IMP5115CDT | 制造商:IMP 制造商全稱(chēng):IMP 功能描述:9-Line SCSI Ter erminat minator |
| IMP5115CDW | 制造商:IMP 制造商全稱(chēng):IMP 功能描述:9-Line SCSI Ter erminat minator |
| IMP5115CDWT | 制造商:IMP 制造商全稱(chēng):IMP 功能描述:9-Line SCSI Ter erminat minator |
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