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參數(shù)資料
| 型號： | IMP2119 |
| 廠商： | IMP INC. |
| 英文描述： | 9-Line ULTRA3 LVD/SE SCSI Terminator |
| 中文描述： | 9線個Ultra3內(nèi)徑/東南的SCSI終結(jié)者 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大?。?/td> | 447K |
| 代理商： | IMP2119 |
Key Features
N
Auto-selectable LVD or single-ended termination
N
3.0pF maximum disabled output capacitance
N
Fast response, no external capacitors required
N
Compatible with active negation drivers
N
15μA supply current in disconnect mode
N
Logic command disconnects all termination lines
N
DIFFSENSE line driver
N
Ground driver integrated for single-ended
operation
N
Current limit and thermal protection
N
Hot-swap compatible (single-ended)
N
Compatible with SCSI, SPI-2, SPI-3, SPI-4
ULTRA160 and ULTRA320
N
Pin compatible with DS2119
Block Diagram
9-Line UL
SCSI T
er
er
The IMP2119 is a multimode SCSI terminator that conforms to the SCSI
Parallel Interconnect-2 (SPI-2) specification developed by the T10 stan-
dards committee for low voltage differential (LVD) termination.
Multimode compatibility permits the use of legacy devices on the bus
without hardware alterations. Automatic mode selection is achieved
through voltage detection on the diffsense line.
TRA3 L
minat
or
VD/SE
The IMP2119 delivers the ultimate in SCSI bus performance while saving
component cost and board area. Elimination of the external capacitors
also mitigates the need for a lengthy capacitor selection process. The indi-
vidual high bandwidth drivers also maximize channel separation and
reduce channel to channel noise and cross talk. The high bandwidth
architecture insures ULTRA3 performance.
When the IMP2119 is enabled, the differential sense (DIFFSENSE) pin
supplies a voltage between 1.2V and 1.4V. In application, this pin is tied
to the DIFFSENSE input of the corresponding LVD transceivers. This
action enables the LVD transceiver function. DIFFSENSE is capable of
supplying a maximum of 15mA. Tying the DIFFSENSE pin HIGH places
the IMP2119 in a high impedance state indicating the presence of an
HVD device. Tying the pin LOW places the part in a single-ended mode
while also signaling the multimode transceiver to operate in a single-
ended mode.
Recognizing the needs of portable and configurable peripherals, the
IMP2119 have a TTL compatible sleep/ disable mode. During this
sleep/ disable mode, power dissipation is reduced to a meager 15
μ
A
while also placing all outputs in a high impedance state. Also during
sleep/ disable mode, the DIFFSENSE function is disabled
and is placed in a high impedance state.
Another key feature of the IMP2119 is the master/ slave
function. Driving this pin HIGH or floating the pin enables
the 1.3V DIFFSENSE reference. Driving the pin LOW dis-
ables the on board DIFFSENSE reference and enables use
of an external master reference device.
Power ON & MODE Delay
Internal V
REF
1.30V
LVD
1.25V
200
52.5
1.07mA
1.07mA
20
52.5
SE
2.2V
Power ON
Power ON
SE 2.85V, 22.5mA
Latch
SE
DISC/HVD
LVD
SE
LVD(-) / SE
1 of 9
LVD(+) / SE
(Pseudo-GND)
SE
HVD
LVD
HVD
DIFF
_CAP
DIFFSENSE
M/S
ISO
TPWR
LVD
Window
Comp.
LVD
SE
10mA
HVD
20k
MODE Control & Delay
5241/42 01 eps
IMP2
1
1
9
2002 IMP, Inc.
Data Communications
1
D
ATA
C
OMMUNICATIONS
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