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參數(shù)資料
| 型號： | IMP1232LPSN-2 |
| 廠商： | IMP INC. |
| 英文描述： | 5V レP Power Suppl er Supply Monit y Monitor and or and Reset Cir eset Circuit |
| 中文描述： | 5V的レ冪p Suppl呃供應(yīng)Monit輜或監(jiān)控和復(fù)位循環(huán)線eset感到電路 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大?。?/td> | 104K |
| 代理商： | IMP1232LPSN-2 |
1999 IMP, Inc.
408-432-9100/ www.impweb.com
1
Key Features
N
Pin compatible with the Dallas Semiconductor
DS1232LP/1232LPS
— 40% lower supply current
N
5V supply monitor
N
Selectable watchdog period
N
Debounce manual push-button reset input
N
Precision temperature-compensated voltage
reference and comparator
N
Power-up, power-down and brownout detection
N
250ms reset time
N
Active LOW open-drain reset and active HIGH
push-pull output
N
Selectable trip point tolerance: 5% or 10%
N
Low-cost, surface mount packages: 8/16-pin
SO, 8-pin DIP and 8-pin MicroSO
N
Wide operating temperature –40
°
C to +85
°
C
(N/EPA suffixed devices)
Block Diagram
RESET
PBRST
1 (2)
1232_03.eps
40k
TOL
IMP1232LP/LPS
(16-Pin Package)
3 (6)
V
CC
–
+
5%/10% Tolerance
Selection
Reference
V
CC
8 (15)
RESET
5 (9)
TD
Push Button
Debounce
2 (4)
Watchdog
Timebase Selection
GND
4 (8)
Reset &
Watchdog Timer
6 (11)
ST
7 (13)
Watchdog
Transition Detector
IMP1
232LP/LPS
P
OWER
M
ANAGEMENT
5V
μ
μ
R
R
eset Cir
– Select
and W
– Push-Butt
The IMP1232LP/ LPS microprocessor supervisor can halt and restart a
“hung-up” or “stalled” microprocessor, restart a microprocessor after a
power failure, and debounce and interface a manual push-button micro-
processor reset switch. The low-power supervisors feature 40% lower
supply current than the pin compatible Dallas Semiconductor
DS1232LP/ LPS.
Precision temperature compensated reference and comparator circuits
monitor the 5V, V
CC
input voltage. During power-up or when the V
CC
power supply falls outside selectable tolerance limits, both the RESET
and RESET become active. When V
CC
rises above the threshold voltage,
the reset signals remain active for an additional 250ms minimum,
allowing the power supply and system microprocessor to stabilize. The
trip point tolerance signal, TOL, selects the trip level tolerance to be
either 5- or 10-percent.
Each device has both a push-pull, active HIGH reset output and an open
drain, active LOW reset output.
A debounced manual reset input activates the reset outputs for a mini-
mum period of 250ms.
Also included is a watchdog timer to stop and restart a microprocessor
that is “hung-up”. Three watchdog time-out periods are selectable:
P P
o
o
w
w
er Suppl
cuit
able T
r
r
i
i
p
p
-P
-P
atc
hdog P
er
er
on R
y Monit
or and
oint T
iod
eset
oler
ance
150ms, 610ms and 1,200ms. If the ST input is not strobed
LOW before the time-out period expires, a reset is issued.
Devices are available in 8-pin DIP, 8/ 16-pin SO and com-
pact 8-pin MicroSO packages.
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