參數(shù)資料
型號： IMIZ9975
英文描述： Clocks and Buffers
中文描述： 時(shí)鐘和緩沖器
文件頁數(shù)： 4/9頁
文件大小： 50K
代理商： IMIZ9975
3.3V, 180MHz, Multi-Output Zero Delay Buffer
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07084 Rev. *B
12/22/2002
Page 4 of 9
Z9951
AC Parameters
1
SYMBOL
Tr / Tf
Fref
FrefDC
Fvco
Tlock
Tr / Tf
Fout
PARAMETER
TCLK Input Rise / Fall
Reference Input Frequency
Reference Input Duty Cycle
PLL VCO Lock Range
Maximum PLL lock Time
Output Clocks Rise / Fall Time
4,5
Maximum Output Frequency
MIN
TYP
MAX
3.0
Note 2
75
480
10
1.0
180
120
60
UNITS
ns
MHz
%
MHz
ms
ns
MHz
CONDITIONS
Note 2
25
200
0.10
-
0.8V to 2.0V
QA = (
÷
2)
QA/QB = (
÷
4)
QB = (
÷
8)
FoutDC
Output Duty Cycle
4,5
TCYCLE/2 –
1
TCYCLE/2 + 1
ns
tpZL, tpZH
tpLZ, tpHZ
TCCJ
Tpd
Output enable time (all outputs)
Output disable time (all outputs)
Cycle to Cycle Jitter (peak to peak)
4,5
TCLK to FB_IN Delay
3
PECL_CLK to FB_IN Delay
3
Any Output to Any Output Skew
4,5
6
7
ns
ns
ps
ps
ps
ps
+/- 100
250
-770
200
50
-950
-
400
-600
350
Fref = 50MHz,
Feedback = VCO/8
TSKEW0
VDD = VDDC = 3.3V +/- 5%, TA = -40
°
C to +85
°
C
Note 1:
Parameters are guaranteed by design and characterization. Not 100% tested in production.
Note 2:
Maximum and minimum input reference is limited by the VCO lock range.
Note 3:
The Tpd window is specified for a 50MHz input reference clock. The window will enlarge/reduce proportionally from the
minimum limits with an increase/decrease of the input reference clock period.
Note 4:
Driving series or parallel terminator 50
(or 50
to VDD/2) transmission lines.
Note 5:
Outputs loaded with 30pF each
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