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參數(shù)資料
| 型號(hào)： | IMIZ9104DAB |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, 1 MM HEIGHT, PLASTIC, TQFP-32 |
| 文件頁(yè)數(shù)： | 3/7頁(yè) |
| 文件大?。?/td> | 120K |
| 代理商： | IMIZ9104DAB |
Z9104
Document #: 38-07083 Rev. *C
Page 3 of 7
Output Clock Disable and Enable Timing
When each clock enable pin (SC25 through SC6) is brought
to a logic low level, its related output clock (CLK25 through
CLK6) will be forced to a logic low level after one complete
cycle. The enable pins are synchronized to the internal clock
such that upon assertion, these signals will hold the clocks low
until the beginning of a new clock period and thus avoid a runt
pulse generation on the outputs.
Figure 2 shows the recommended power supply decoupling
circuitry to obtain minimum device clock noise (jitter). Designs
shown implements this decoupling scheme in noisy VDD
environments to protect the device’s internal analog circuitry
from digital noise generated on the main 3.3V supply. A range
of 2.2 to 15 Ohms is recommended for Rs. Rs should be
adjusted to the minimum value required to produce acceptable
performances from the device. The ultimate limitation on the
Rs maximum value is the device’s minimum VDD spec.
Applications Examples
Fig. 2
Stop on next falling edge
Start on next
rising edge
CLKx
SCx
CLK
Figure 1.
VDDA
+
-
3.3V
.01
F
22
F
Z9104
Device
R
s
Figure 2.
Table 2. Z9104 Input Reference Frequency Ranges
Mode
FBS1
FBS0
REFIN Frequency
Min. (MHz)
REFIN Frequency
Max. (MHz)
CLK(25:6), Output
Frequency (MHz)
Example
1
0
50
120
1 x REFIN
REFIN = 66.7 MHz
CLK* = 66.7 MHz
1
0
1
40
96
1.25 x REFIN
REFIN = 66.7 MHz
CLK* = 83.3 MHz
1
0
33.3
80
1.5 x REFIN
REFIN = 66.7 MHz
CLK* = 100 MHz
1
25
60
1 x REFIN
REFIN = 33.3 MHz
CLK* = 33.3 MHz
0
25
60
2 x REFIN
REFIN = 33.3 MHz
CLK* = 66.7 MHz
0
1
20
48
2.5 x REFIN
REFIN = 33.3 MHz
CLK* = 83.3 MHz
0
1
0
16.7
40
3 X REFIN
REFIN = 33.3 MHz
CLK* = 100 MHz
0
1
16.7
40
1.5 X REFIN
REFIN = 33.3 MHz
CLK* = 50 MHz
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