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參數(shù)資料
| 型號： | IMIC9835CTT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | Low-EMI Clock Generator for Intel Mobile 133-MHz/3 SO-DIMM Chipset Systems |
| 中文描述： | 133.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 6 X 14 MM, TSSOP2-56 |
| 文件頁數(shù)： | 1/18頁 |
| 文件大?。?/td> | 343K |
| 代理商： | IMIC9835CTT |
Low-EMI Clock Generator for Intel
Mobile 133-MHz/3 SO-DIMM Chipset Systems
C9835
Cypress Semiconductor Corporation
Document #: 38-07303 Rev. **
3901 North First Street
San Jose
CA 95134
408-943-2600
Revised April 5, 2002
Features
Meets Intel’s
Mobile 133.3MHz Chipset
Three CPU Clocks (66.6/100/133.3 MHz, 2.5V)
Six SDRAM Clocks, 1-DCLK (100/133.3 MHz, 3.3V)
Seven PCI Clocks (33MHz, 3.3V), one free running
Two IOAPIC clocks, synchronous to CPU clock (33.3
MHz, 2.5V)
One REF Clock
Two 48-MHz fixed non-SSCG clocks (USB and DOT)
Three 3V66 clocks (66.6 MHz, 3.3V) ICH, HUBLINK, and
AGP memory
One selectable frequency for VCH video channel clock
(48-MHz non-SSCG, 66.6-MHz CPU-SSCG, 3.3V)
Power management using power-down, CPU stop, and
PCI stop pins
Three function select pins (include test-mode select)
Cypress Spread Spectrum for best electromagnetic
interference (EMI) reduction
SMBUS support with readback
56-pin SSOP and TSSOP packages
Note:
1.
These are the frequencies that are selectable after power up using the SEL1 and SEL0 hardware pins. Other frequencies may be chosen using the devices
SMBUS interface. See the expanded frequency for a complete listing of all of the availible frequencies.
Will be set to 133MHz, when SMBUS Byte3, Bit 0 is set to logic 1.
2.
Table 1. Function Table
[1]
TEST#
SEL1
SEL0
CPU(0:2)
SDRAM(0:5)
DCLK
Hi-Z
TCLK/2
100.0
[2]
100.0
[2]
133.3
100.0
[2]
3V66(0:2)
PCIF(1:6)
48M(0:1)
REF
IOAPIC(0:10)
0
0
1
1
1
1
X
X
0
0
1
1
0
1
0
1
0
1
Hi-Z
TCLK/2
66.6
100.0
133.3
133.3
Hi-Z
TCLK/3
66.6
66.6
66.6
66.6
Hi-Z
TCLK/6
33.3
33.3
33.3
33.3
Hi-Z
TCLK/2
48
48
48
48
Hi-Z
TCLK
14.318
14.318
14.318
14.318
Hi-Z
TCLK/6
33.3
33.3
33.3
33.3
Block Diagram
Pin Configuration
V D D C
V D D S
V D D
V D D P
V D D I
V D D
V D D S
P L L 1
R in
i2 c -c lk
i2 c -d a ta
IO A P IC
tris ta te
s 0
P D #
C P U
S D R A M
3 V 6 6
P C I
P L L 2
R in
4 8
P D #
i2 c -c lk
3 6 p F
3 6 p F
3
6
3
6
2
2
1
1
V D D
X IN
X O U T
C P U (0 :2 )
S D R A M (0 :5 )
3 V 6 6 (0 :2 )
P C I(1 :6 )
IO A P IC (0 ,1 )
S D A T A
S C L K
P D #
S E L 0 ,1
T E S T #
4 8 M (0 ,1 )
D C L K
R E F
V C H _ C L K
C P U _ S T P #
P C I_ S T P #
1
V D D
V D D P
P C I_ F
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
XIN
VDD
SEL1
XOUT
VSS
VSS
3V66_0
3V66_1
3V66_2(AGP)
PCI_F
PCI1
VSS
PCI2
PCI3
VDDP
PCI4
PCI5
PCI6
VDD
VSS
AVDD
AVSS
VSS
TEST#
PD#
CPU_STP#
VDD
VCH_CLK
VDDS
SDRAM5
DCLK
VSS
SDRAM4
SDRAM2
SDRAM3
VDDS
SDRAM0
SDRAM1
VSS
CPU2
VSS
CPU1
VDDC
CPU0
VDDI
IOAPIC1
IOAPIC0
VSS
C
9
8
3
5
REF
48M0(USB)
48M1(DOT)
VDD
SEL0
SDATA
SCLK
49
50
51
52
53
54
55
56
PCI_STP#
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