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參數(shù)資料
| 型號(hào)： | IMIC9827H |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時(shí)鐘和緩沖器 |
| 文件頁(yè)數(shù)： | 8/10頁(yè) |
| 文件大?。?/td> | 125K |
| 代理商： | IMIC9827H |
C9530
Document #: 38-07033 Rev. *B
Page 8 of 10
Test and Measurement Set-up
T
R
/ T
F
XIN Rise and Fall Times
Measured between 0.3V
DD
and 0.7V
DD
As an average over 1
μ
s
duration
Over 150 ms
–
10.0
ns
T
CCJ
XIN Cycle to Cycle Jitter
–
500
ps
L
ACC
CLK
T
DC
T
PERIOD33
T
PERIOD66
T
PERIOD100
T
PERIOD133
T
R
/ T
F
Long-term Accuracy
300
ppm
CLK Duty Cycle
33MHz CLK Period
66MHz CLK Period
100MHz CLK Period
133MHz CLK Period
CLK Rise and Fall Times
Measurement at 1.5V
Measurement at 1.5V
Measurement at 1.5V
Measurement at 1.5V
Measurement at 1.5V
Measured between 0.4V and
2.4V
Measurement at 1.5V
Measurement at 1.5V
45
29.5
14.5
9.5
7.0
0.5
55
30.5
15.5
10.5
8.0
2.0
%
ns
ns
ns
ns
ns
T
SKEW
T
CCJ
REF
T
DC
Any CLK to Any CLK Clock Skew
CLK Cycle to Cycle Jitter
–
–
250
175
ps
ps
REF Duty Cycle
Measurement at 1.5V
Measured between 0.4V and
2.4V
Measurement at 1.5V
45
1.0
55
4.0
%
ns
T
R
/ T
F
REF Rise and Fall Times
T
CCJ
ENABLE/DISABLE and SET-UP
tpZL,tpZH
tpLZ,tpZH
T
STABLE
REF Cycle to Cycle Jitter
–
750
ps
Output Enable Delay (all outputs)
Output Disable Delay (all outputs)
Clock Stabilization from Power-up
–
–
–
10.0
10.0
3.0
ns
ns
ms
AC Electrical Specifications
(continued)
Parameter
Description
Condition
Min.
Max.
Unit
2 .4 V
0 .4 V
3 .3 V
0 V
T r
T f
1 .5 V
3 .3 V S ig n a ls
tD C
-
-
Probe
Output under Test
Load Cap
Lumped Load
LVTTL Signaling
Figure 2. Test and Measurement Set-up
Table 8. Loading
Output Name
CLK5
REF
Max Load (in pF)
30
20
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