
491
11028E–ATARM–22-Apr-13
SAM9G46
Multi-master transmitter mode
Multi-master receiver mode
Slave transmitter mode
Slave receiver mode
These modes are described in the following chapters.
31.8
Master Mode
31.8.1
Definition
The Master is the device that starts a transfer, generates a clock and stops it.
31.8.2
Application Block Diagram
Figure 31-5. Master Mode Typical Application Block Diagram
31.8.3
Programming Master Mode
The following registers have to be programmed before entering Master mode:
1.
DADR (+ IADRSZ + IADR if a 10 bit device is addressed): The device address is used
to access slave devices in read or write mode.
2.
CKDIV + CHDIV + CLDIV: Clock Waveform.
3.
SVDIS: Disable the slave mode.
4.
MSEN: Enable the master mode.
31.8.4
Master Transmitter Mode
After the master initiates a Start condition when writing into the Transmit Holding Register,
TWI_THR, it sends a 7-bit slave address, configured in the Master Mode register (DADR in
TWI_MMR), to notify the slave device. The bit following the slave address indicates the transfer
direction, 0 in this case (MREAD=0inTWI_MMR).
The TWI transfers require the slave to acknowledge each received byte. During the acknowl-
edge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull
it down in order to generate the acknowledge. The master polls the data line during this clock
pulse and sets the Not Acknowledge bit (NACK) in the status register if the slave does not
Host with
TWI
Interface
TWD
TWCK
Atmel TWI
Serial EEPROM
IC RTC
IC LCD
Controller
Slave 1
Slave 2
Slave 3
VDD
IC Temp.
Sensor
Slave 4
Rp: Pull up value as given by the IC Standard
Rp