參數(shù)資料
型號: IDTSSTE32882HLBBKG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 38/73頁
文件大?。?/td> 0K
描述: IC REGISTERING CLK DRIVER 176BGA
標準包裝: 208
類型: 時鐘緩沖器/驅動器,多路復用器
PLL:
主要目的: 存儲器,DDR3,RDIMM
輸入: CMOS
輸出: CMOS
電路數(shù): 1
比率 - 輸入:輸出: 5:60
差分 - 輸入:輸出: 是/是
頻率 - 最大: 810MHz
電源電壓: 1.282 V ~ 1.575 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 176-TFBGA
供應商設備封裝: 176-CABGA(6x15)
包裝: 托盤
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
43
SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
REGISTER CKE POWER DOWN WITH IBT OFF
Upon entry into CKE Power Down mode with IBT off, all register input buffers including IBT are disabled except for CK/CK,
DCKEn, FBIN/FBIN, and RESET. The SSTE32882HLB disables input buffers within tInDIS clocks after latching both
DCKEn Low. In order to eliminate and false parity check error, the PAR_IN input buffer has to be kept active for 1 tCK after
Address and Command input buffers disabled. After tInDIS, the register can tolerate floating input except for CK/CK, DCKEn
and RESET. The SSTE32882HLB also disables all its output buffers except for Yn/Yn, QxODTn, QxCKEn and
FBOUT/FBOUT. The Yn/Yn and FBOUT/FBOUT outputs continue to drive a valid phase accurate clock signal. The
QxODTn and QxCKEn outputs are driven Low. The register output buffers are Hi-Z tQDIS clock after QxCKEn is driven Low.
This is shown in the next figure.
Power Down Mode Entry and Exit with IBT Off
(1) i, j only apply for QuadCS capable register. When QuadCS is enabled, i = 2, j = 3.
(2) QuadCS disabled: During CKE Power Down Entry/Exit, driving DCS[1,0] LOW is illegal as it will force SSTE32882 into
Register Control Word access mode.
(3)Upon CKE Power Down exit, QxCSn will be held HIGH for maximum of 1 tCK regardless of what DCSn input level is. For
all other operation QxCSn outputs will follow DCSn inputs.
H or L
CK
RESET
DAn,DBAn
DRAS,
DODTn
DCKEn
DCAS,
DWE
High or Low
Low
High
tInDIS
High or Low
High
Hi-z
High
Yn
QxAn,
QxODTn
High or Low
Low
High
High or Low
High
Hi-z
QxRAS,
QxCAS,
QxWE
QxCKEn
High or Low
Low
Hi-z
tFixedoutput
Hi-z
tQDIS
Output buffers are Hi-z
n
n-1
n+4
n+8
n+12
n+16
n+20
n
n-1
n+4
n+8
n+12
n+16
n+20
QxBAn
High or Low
High
Hi-z
High
Low
High
Hi-z
High or Low
Low
High or Low
PAR_IN
Hi-z
QxCS[i,0]
QxCS[j,1]
DCS[i,0]
DCS[j,1]
H or L
Either or both DCKEn inputs are driven High
Either or both QxCKEn outputs are driven High
tEN
see Note 3
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