- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄65595 > IDTQS5LV931-80Q8 (INTEGRATED DEVICE TECHNOLOGY INC) PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 PDF資料下載
參數(shù)資料
| 型號(hào)： | IDTQS5LV931-80Q8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 封裝： | QSOP-20 |
| 文件頁(yè)數(shù)： | 1/7頁(yè) |
| 文件大?。?/td> | 49K |
| 代理商： | IDTQS5LV931-80Q8 |
MDSC-00022-00
QUALITY SEMICONDUCTOR, INC.
1
DECEMBER 15, 1997
QS5LV931
Now
an
Company
R
D
Q
Q0
R
D
Q
Q1
R
D
Q
Q2
R
D
Q
Q3
R
D
Q
Q4
R
D
Q
Q/2
Q
0
1
0
/2
VCO
LOOP
FILTER
PHASE
DETECTOR
FREQ_SEL
FEEDBACK
SYNC
PLL_EN
OE/
RST
Figure 1. Functional Block Diagram
FEATURES/BENEFITS
JEDEC LVTTL compatible level
Clock input is 5V tolerant
Q outputs, Q/2 output
< 300ps output skew, Q0-Q4
Outputs 3-state and reset while OE/
RST low
PLL disable feature for low frequency testing
Internal loop filter RC network
Internal VCO/2 option
Balanced drive outputs
± 24mA
80MHz maximum frequency
Industrial temperature range
Available in space saving QSOP package
DESCRIPTION
The QS5LV931 Clock Driver uses an internal phase
locked loop (PLL) to lock low skew outputs to a
reference clock input. Six outputs are available:
Q0-Q4, Q/2. Careful layout and design ensure
< 300ps skew between the Q0-Q4, and Q/2 outputs.
The QS5LV931 includes an internal RC filter which
provides excellent jitter characteristics and eliminates
the need for external components. Various combina-
tions of feedback and a divide-by-2 in the VCO path
allow applications to be customized for linear VCO
operation over a wide range of input SYNC frequen-
cies. The PLL can also be disabled by the PLL_EN
signal to allow low frequency or DC testing. The
QS5LV931 is designed for use in cost sensitive high-
performance computing systems, workstations, multi-
board computers, networking hardware, and main-
frame systems. Several can be used in parallel or
scattered throughout a system for guaranteed low
skew, system-wide clock distribution networks. In the
QSOP package, the QS5LV931 clock driver repre-
sents the best value in small form factor, high-perfor-
mance clock management products.
For more information on PLL clock driver products,
see Application Note AN-22A.
3.3V Low Skew CMOS
PLL Clock Driver With
Integrated Loop Filter
QS5LV931
Q
QUALITY
SEMICONDUCTOR, INC.
Q
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDTQS74FCT153ATSO8 | FCT SERIES, DUAL 4 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDSO16 |
| IDTQS74FCT158ATQ8 | FCT SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, INVERTED OUTPUT, PDSO16 |
| IDTQS74FCT2157CTQ8 | FCT SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDSO16 |
| IDTQS74FCT2245ATSO8 | FCT SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO20 |
| IDTQS74FCT2257ATS18 | FCT SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDSO16 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDTQS74153ATQ | 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:HIGH-SPEED CMOS DUAL 4-INPUT MULTIPLEXER |
| IDTQS74153ATSO | 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:HIGH-SPEED CMOS DUAL 4-INPUT MULTIPLEXER |
| IDTQS74153CTQ | 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:HIGH-SPEED CMOS DUAL 4-INPUT MULTIPLEXER |
| IDTQS74153CTSO | 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:HIGH-SPEED CMOS DUAL 4-INPUT MULTIPLEXER |
| IDTQS74253ATQ | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:4-Input Digital Multiplexer |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。