Figure 2. Pin Assignment VREF IN1+ IN1- GS1 GND OSCIN " />
參數(shù)資料
型號(hào)： IDTNW6005AS
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 12/20頁(yè)
文件大?。?/td> 0K
描述： IC CALLER ID DECODER 20-SOIC
標(biāo)準(zhǔn)包裝： 37
類(lèi)型： 來(lái)電身份解碼器
應(yīng)用： 傳真，調(diào)制解調(diào)器，尋呼機(jī)
電壓 - 電源，模擬： 2.5 V ~ 3.8 V
電壓 - 電源，數(shù)字： 2.5 V ~ 3.8 V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 20-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 20-SOIC
包裝： 管件
其它名稱(chēng)： NW6005AS
2
INDUSTRIAL TEMPERATURE RANGE
NW6005 ENHANCED TYPE II CALLER ID DECODER
PIN INFORMATION
Figure 2. Pin Assignment
VREF
IN1+
IN1-
GS1
GND
OSCIN
OSCOUT
CB0
DCLK
DATA
IN2+
IN2-
GS2
CB2
CB1
VCC
CD
ST/GT
EST
DR/STD
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
Name
Type
Pin No.
Description
VREF
O
1
Reference Voltage.
This output is used to bias the input OP amp. It is typically VCC/2.
IN1+
I
2
Non-inverting Input of the gain adjustable Tip/Ring OP amp.
IN1-
I
3
Inverting Input of the gain adjustable Tip/Ring OP amp.
GS1
O
4
Gain Select Output of the gain adjustable Tip/Ring OP amp.
The Tip/Ring signal can be attenuated or amplified at GS1 by adjusting the feedback resistor between GS1 and
IN1-. The FSK signal is always detected by Tip/Ring OP amp while DT-AS signal can be detected by either
Tip/Ring or Hybrid OP amp. The OP amp selection is controlled by CB1 and CB2 pins.
GND
-
5
Ground.
OSCIN
I
6
Oscillator Input.
A 3.579545 MHz crystal or ceramic resonator should be connected between this pin and the OSCOUT. It can also
be driven by an external clock source.
OSCOUT
O
7
Oscillator Output.
A 3.579545 MHz crystal or ceramic resonator should be connected between this pin and the OSCIN. When an
external clock drives OSCIN, this pin can be left floating.
CB0
I
8
Control Bit 0 (FSK Data Interface Mode Select).
This pin can select the 3-wire FSK data interface mode. A ‘0’ on this pin indicates interface mode 0; while a ‘1’ on
this pin indicates interface mode 1. (The FSK data interface is consisted of DATA, DCLK and DR/STD pins.)
When CB0 is high and CB1, CB2 are both low, the device is set into the power down state.
DCLK
I/NC
9
Data Clock of the Serial FSK Interface.
In mode 0 (CB0 is low), this pin is unused; In mode 1 (CB0 is high), this pin is an input which clock the FSK data
byte out to the DATA pin.
DATA
O
10
Data Output of the Serial FSK Interface.
In mode 0 (CB0 is low), the FSK serial bit stream is output to the DATA pin directly.
In mode 1 (CB0 is high), the start bit is stripped off, the data byte and the stop bit is stored in a 9-bit buffer. At the
end of each word signaled by the DR/STD pin, the microcontroller should shift the byte out onto the DATA pin by
applying 8 read pulses to the DCLK pin. A 9th DCLK pulse will shift out the stop bit for framing error checking.
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