Figure 12. IDT82V3255 Power Decoupling Scheme<" />
參數(shù)資料
型號： IDT82V3255TFG8
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 69/132頁
文件大小： 0K
描述： IC PLL WAN SMC STRATUM 3 64-TQFP
標準包裝： 1,250
類型： 時鐘/頻率發(fā)生器，多路復用器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS，LVDS，PECL
輸出： CMOS，LVDS，PECL
電路數(shù)： 1
比率 - 輸入:輸出： 3:3
差分 - 輸入:輸出： 是/是
頻率 - 最大： 622.08MHz
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應商設備封裝： 64-TQFP（10x10）
包裝： 帶卷 (TR)
其它名稱： 82V3255TFG8
IDT82V3255
WAN PLL
Functional Description
41
December 3, 2008
3.16
POWER SUPPLY FILTERING TECHNIQUES
Figure 12. IDT82V3255 Power Decoupling Scheme
To achieve optimum jitter performance, power supply filtering is
required to minimize supply noise modulation of the output clocks. The
common sources of power supply noise are switch power supplies and
the high switching noise from the outputs to the internal PLL. The
82V3255 provides separate VDDA power pins for the internal analog
PLL, VDD_DIFF for the differential output driver circuit and VDDD pins
for the core logic as well as I/O driver circuits.
To minimize switching power supply noise generated by the switch-
ing regulator, the power supply output should be filtering with sufficient
bulk capacity to minimize ripple and 0.1 uF (0402 case size, ceramic)
caps to filter out the switching transients.
For the 82V3255, the decoupling for VDDA, VDD_DIFF and VDDD
are handled individually. VDDD, VDD_DIFF and VDDA should be indi-
vidually connected to the power supply plane through vias, and bypass
capacitors should be used for each pin. Figure 12 illustrated how bypass
capacitor and ferrite bead should be connected to power pins.
The analog power supply VDDA and VDD_DIFF should have low
impedance. This can be achieved by using one 10 uF (1210 case size,
ceramic) and at least four 0.1 uF (0402 case size, ceramic) capacitors in
parallel. The 0.1 uF (0402 case size, ceramic) capacitors must be
placed right next to the VDDA and VDD_DIFF pins as close as possible.
Note that the 10 uF capacitor must be of 1210 case size, and it must be
ceramic for lowest ESR (Effective Series Resistance) possible. The 0.1
uF should be of case size 0402, this offers the lowest ESL (Effective
Series Inductance) to achieve low impedance towards the high speed
range.
For VDDD, at least ten 0.1 uF (0402 case size, ceramic) and one 10
uF (1210 case size, ceramic) capacitors are recommended. The 0.1 uF
capacitors should be placed as close to the VDDD pins as possible.
Please refer to evaluation board schematic for details.
IDT 82 V3255
3. 3V
0.1
F
10
F
DGND
AGND
GND_DIFF
1, 3, 15, 58
VDDA
VDDD
0.1
F
3.3V
10
F
21
7, 10, 11, 31, 40, 53
4, 14, 57
VDD _DIFF
22
8, 9, 12, 32, 36, 38, 39, 45, 46 , 54
0.1
F
0.1
F0.1 F
0.1
F
0.1
F0.1 F0.1 F
0.1
F
0.1
F0.1 F0.1 F0.1 F
SLF7028T-100M1R1
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相關代理商/技術參數(shù)
參數(shù)描述
IDT82V3255TFGBLANK 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL
IDT82V3280 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL
IDT82V3280_08 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL
IDT82V3280APFG 功能描述:IC PLL WAN SE STRATUM 2 100TQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT
IDT82V3280APFG8 制造商:Integrated Device Technology Inc 功能描述:IC PLL WAN SE STRATUM 2 100TQFP
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