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參數(shù)資料
| 型號(hào)： | IDT82V3202NLG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 114/117頁(yè) |
| 文件大小： | 0K |
| 描述： | IC PLL WAN EBU SGL 68-VFQFPN |
| 標(biāo)準(zhǔn)包裝： | 21 |
| 類型： | 時(shí)鐘/頻率發(fā)生器，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum |
| 輸入： | CMOS |
| 輸出： | CMOS，LVDS，PECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 無(wú)/是 |
| 頻率 - 最大： | 622.08MHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 68-VFQFPN（10x10） |
| 包裝： | 托盤 |
| 其它名稱： | 82V3202NLG |
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IDT82V3202
EBU WAN PLL
Programming Information
96
September 11, 2009
7.4
VFQFPN EPAD THERMAL RELEASE PATH
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on the
Printed Circuit Board (PCB) within the footprint of the package corre-
sponding to the exposed metal pad or exposed heat slug on the pack-
age, as shown in Figure 19. The solderable area on the PCB, as defined
by the solder mask, should be at least the same size/shape as the
exposed pad/slug area on the package to maximize the thermal/electri-
cal performance. Sufficient clearance should be designed on the PCB
between the outer edges of the land pattern and the inner edges of pad
pattern for the leads to avoid any shorts.
Figure 19. Assembly for Expose Pad thermal Release Path (Side View)
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a solder
joint, thermal vias are necessary to effectively conduct from the surface
of the PCB to the ground plane(s). The land pattern must be connected
to ground through these vias. The vias act as ‘heat pipes’. The number
of vias (i.e. ‘heat pipes’) are application specific and dependent upon the
package power dissipation as well as electrical conductivity require-
ments. Thus, thermal and electrical analysis and/or testing are recom-
mended to determine the minimum number needed. Maximum thermal
and electrical performance is achieved when an array of vias is incorpo-
rated in the land pattern. It is recommended to use as many vias con-
nected to ground as possible. It is also recommended that the via
diameter should be 12 to 13mils (0.30 to 0.33mm) with 1 oz copper via
barrel plating. This is desirable to avoid any solder wicking inside the via
during the soldering process which may result in voids in solder between
the exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern.
Note: These recommendations are to be used as a guideline only.
For further information, please refer to the Application Note on the Sur-
face Mount Assembly of Amkor's Thermally/Electrically Enhance Lead
fame Base Package, Amkor Technology.
THERMAL VIA
LAND PATTERN
SOLDER
PIN
SOLDER
PIN PAD
PIN
GROUND PLANE
EXPOSED HEAT SLUG
(GROUND PAD)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT82V3202NLG8 | 功能描述:IC PLL WAN EBU SGL 68-VFQFPN RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| IDT82V3202NLGBLANK | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:EBU WAN PLL |
| IDT82V3255 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL |
| IDT82V3255_08 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL |
| IDT82V3255DK | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL |
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