Figure-20 JTAG State Diagram<" />
參數(shù)資料
型號(hào): IDT82V2052EPFG8
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 51/70頁(yè)
文件大?。?/td> 0K
描述: IC LIU E1 2CH SHORT HAUL 80-TQFP
標(biāo)準(zhǔn)包裝: 750
類型: 線路接口裝置(LIU)
規(guī)程: E1
電源電壓: 3.13 V ~ 3.47 V
安裝類型: 表面貼裝
封裝/外殼: 80-LQFP
供應(yīng)商設(shè)備封裝: 80-TQFP(14x14)
包裝: 帶卷 (TR)
其它名稱: 82V2052EPFG8
IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
IEEE STD 1149.1 JTAG TEST ACCESS PORT
55
December 12, 2005
Figure-20 JTAG State Diagram
Exit2-IR
This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-IR
state, which terminates the scanning process. If TMS is held low and a rising edge is applied to TCK, the controller enters the Shift-IR state.
The test data register selected by the current instruction retains its previous value and the instruction does not change during this state.
Update-IR
The instruction shifted into the instruction register is latched into the parallel output from the shift-register path on the falling edge of TCK.
When the new instruction has been latched, it becomes the current instruction. The test data registers selected by the current instruction retain
their previous value.
Table-44 TAP Controller State Description (Continued)
STATE
DESCRIPTION
Test-logic Reset
Run Test/Idle
Select-DR
Select-IR
Capture-DR
Capture-IR
Shift-DR
Shift-IR
Exit1-DR
Exit1-IR
Pause-DR
Pause-IR
Exit2-DR
Exit2-IR
Update-DR
Update-IR
1
0
1
00
0
1
0
1
0
1
0
1
0
1
0
1
0
1
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